Texas Instruments TMS320F2837 D Series Manual de usuario

SPRZ412K–December 2013–Revised February 2020

TMS320F2837xD Dual-Core MCUs Silicon Revisions C, B, A, 0

Silicon Errata

SPRZ412K–December 2013–Revised February 2020

TMS320F2837xD Dual-Core MCUs

Silicon Revisions C, B, A, 0

1 Introduction

This document describes the silicon updates to the functional specifications for the TMS320F2837xD

microcontrollers (MCUs).

The updates are applicable to the following:

• 337-ball New Fine Pitch Ball Grid Array, ZWT Suffix

• 176-pin PowerPAD™ Thermally Enhanced Low-Profile Quad Flatpack, PTP Suffix

2 Device and Development Support Tool Nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all

[TMS320] DSP devices and support tools. Each TMS320™ DSP commercial family member has one of

three prefixes: TMX, TMP, or TMS (for example, TMS320F28379D). Texas Instruments recommends two

of three possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent

evolutionary stages of product development from engineering prototypes (with TMX for devices and TMDX

for tools) through fully qualified production devices and tools (with TMS for devices and TMDS for tools).

TMX Experimental device that is not necessarily representative of the final device's electrical

specifications

TMP Final silicon die that conforms to the device's electrical specifications but has not

completed quality and reliability verification

TMS Fully qualified production device

Support tool development evolutionary flow:

TMDX Development-support product that has not yet completed Texas Instruments internal

qualification testing

TMDS Fully qualified development-support product

TMX and TMP devices and TMDX development-support tools are shipped against the following

disclaimer:

"Developmental product is intended for internal evaluation purposes."

TMS devices and TMDS development-support tools have been characterized fully, and the quality and

reliability of the device have been demonstrated fully. TI's standard warranty applies.

Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard

production devices. Texas Instruments recommends that these devices not be used in any production

system because their expected end-use failure rate still is undefined. Only qualified production devices are

to be used.

TI device nomenclature also includes a suffix with the device family name. This suffix indicates the

package type (for example, PTP) and temperature range (for example, T).

PREFIX

TMS

TMX = experimental device

TMP = prototype device

TMS = qualified device

320

DEVICE FAMILY

320 = TMS320 MCU Family

TECHNOLOGY

F = Flash

28379D

DEVICE

28379D

28377D

28376D

28375D

28374D

28378D

PTP

PACKAGE TYPE

176

337-Ball ZWT New Fine Pitch Ball Grid Array (nFBGA)

-Pin PTP PowerPAD Thermally Enhanced Low-Profile Quad Flatpack (HLQFP)

100-Pin PZP PowerPAD Thermally Enhanced Thin Quad Flatpack (HTQFP)

TEMPERATURE RANGE

−40°C to 105°C (T )

−40°C to 125°C (T )

(Q refers to AEC Q100 qualification for automotive applications.)

YMLLLLS

LLLL

Lot Trace Code

2-Digit Year/Month Code

Assembly Lot

Assembly Site Code

Wafer Fab Code as applicable

Silicon Revision Code

Green (Low Halogen and RoHS-compliant)

$$#-YMLLLLS

F28379DPTPT

TMS320

Package

Pin 1

Device Markings

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3 Device Markings

Figure 1 provides an example of the 2837xD device markings and defines each of the markings. The

device revision can be determined by the symbols marked on the top of the package as shown in

Figure 1. Some prototype devices may have markings different from those illustrated. Figure 2 shows an

example of the device nomenclature.

Figure 1. Example of Device Markings

(1) Silicon Revision ID

Table 1. Determining Silicon Revision From Lot Trace Code

SILICON REVISION CODE SILICON REVISION REVID(1)

Address: 0x5D00C COMMENTS

Blank 0 0x0000 This silicon revision is available as TMX.

A A 0x0000 This silicon revision is available as TMX.

B B 0x0002 This silicon revision is available as TMX.

C C 0x0003 This silicon revision is available as TMS.

Figure 2. Example of Device Nomenclature

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Usage Notes and Known Design Exceptions to Functional Specifications

SPRZ412K–December 2013–Revised February 2020

TMS320F2837xD Dual-Core MCUs Silicon Revisions C, B, A, 0

4 Usage Notes and Known Design Exceptions to Functional Specifications

4.1 Usage Notes

Usage notes highlight and describe particular situations where the device's behavior may not match

presumed or documented behavior. This may include behaviors that affect device performance or

functional correctness. These usage notes will be incorporated into future documentation updates for the

device (such as the device-specific data sheet), and the behaviors they describe will not be altered in

future silicon revisions.

Table 2 shows which silicon revision(s) are affected by each usage note.

Table 2. List of Usage Notes

TITLE SILICON REVISION(S) AFFECTED

0 A B C

PIE: Spurious Nested Interrupt After Back-to-Back PIEACK Write and Manual CPU

Interrupt Mask Clear Yes Yes Yes Yes

Caution While Using Nested Interrupts Yes Yes Yes Yes

SYS/BIOS: Version Implemented in Device ROM is not Maintained Yes Yes Yes Yes

SDFM: Use Caution While Using SDFM Under Noisy Conditions Yes Yes Yes Yes

4.1.1 PIE: Spurious Nested Interrupt After Back-to-Back PIEACK Write and Manual CPU Interrupt

Mask Clear

Revision(s) Affected: 0, A, B, C

Certain code sequences used for nested interrupts allow the CPU and PIE to enter an inconsistent state

that can trigger an unwanted interrupt. The conditions required to enter this state are:

1. A PIEACK clear is followed immediately by a global interrupt enable (EINT or asm(" CLRC INTM")).

2. A nested interrupt clears one or more PIEIER bits for its group.

Whether the unwanted interrupt is triggered depends on the configuration and timing of the other

interrupts in the system. This is expected to be a rare or nonexistent event in most applications. If it

happens, the unwanted interrupt will be the first one in the nested interrupt's PIE group, and will be

triggered after the nested interrupt reenables CPU interrupts (EINT or asm(" CLRC INTM")).

Workaround: Add a NOP between the PIEACK write and the CPU interrupt enable. Example code is

shown below.

//Bad interrupt nesting code

PieCtrlRegs.PIEACK.all = 0xFFFF; //Enable nesting in the PIE

EINT; //Enable nesting in the CPU

//Good interrupt nesting code

PieCtrlRegs.PIEACK.all = 0xFFFF; //Enable nesting in the PIE

asm(" NOP"); //Wait for PIEACK to exit the pipeline

EINT; //Enable nesting in the CPU

4.1.2 Caution While Using Nested Interrupts

Revision(s) Affected: 0, A, B, C

If the user is enabling interrupts using the EINT instruction inside an interrupt service routine (ISR) in order

to use the nesting feature, then the user must disable the interrupts before exiting the ISR. Failing to do so

may cause undefined behavior of CPU execution.

Usage Notes and Known Design Exceptions to Functional Specifications

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4.1.3 SYS/BIOS: Version Implemented in Device ROM is not Maintained

Revision(s) Affected: 0, A, B, C

The SYS/BIOS version 6.37 in ROM cannot be updated to address bug fixes or enhancements. For

applications using this ROM version of SYS/BIOS, the user should review the release notes on the

SYS/BIOS Product Releases page to assess any application impact to known bugs.

To use the latest maintained SYS/BIOS version, download the SYS/BIOS library and include in the

application flash image instead of using the ROM version.

4.1.4 SDFM: Use Caution While Using SDFM Under Noisy Conditions

Revision(s) Affected: 0, A, B, C

The SDFM clock input (SDx_Cy) directly clocks the SDFM module when there is no GPIO input

synchronization. Any glitches or ringing noise on the SDx_Cy input beyond VIH or VIL can corrupt the

SDFM module, leading to unpredictable results.

Workaround(s):

SDFM GPIO Asynchronous Mode:

Special attention should be taken during board design to ensure a clean and noise-free signal that meets

the SDFM timing requirements. Precautions such as series termination for ringing due to any impedance

mismatch of the clock driver, and spacing of traces from other high-frequency signals are recommended.

SDFM GPIO Qualification (3-sample) Mode:

It is highly recommended that the SDFM GPIO qualification mode be used in noisy conditions. This mode

provides additional protection by filtering both SDx_Cy and SDx_Dy inputs from system noise. Refer to the

"SDFM Timing Requirements When Using GPIO Input Qualification (3-Sample Window)" table in the

TMS320F2837xD Dual-Core Microcontrollers Data Manual when using this option.

When a noise event occurs while using the GPIO Qualification mode, there may still be data disturbance,

but it will be proportional to the duration of the noise event and typically filtered by the oversampling of the

SDFM module. Below is a relative listing of each SDFM mode's sensitivity to data variation in the

presence of severe system noise.

• Mode 0: This mode is the best performing mode. It is the recommended mode under noisy conditions.

• Mode 1 and Mode 3: The error in these modes can be twice as large as the error in Mode 0 since each

noise glitch can introduce error for multiple data bits.

• Mode 2: This option is unavailable when using GPIO qualification. This mode is not recommended for

either GPIO ASYNC or GPIO qualification.

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Usage Notes and Known Design Exceptions to Functional Specifications

SPRZ412K–December 2013–Revised February 2020

TMS320F2837xD Dual-Core MCUs Silicon Revisions C, B, A, 0

4.2 Known Design Exceptions to Functional Specifications

Table 3 shows which silicon revision(s) are affected by each advisory.

Table 3. List of Advisories

TITLE SILICON REVISION(S) AFFECTED

0 A B C

Analog Bandgap References Yes Yes Yes Yes

Analog Trim of Some TMX Devices Yes Yes Yes

ADC: ADC Post-Processing Block Limit Compare Yes Yes Yes Yes

ADC: Interrupts may Stop if INTxCONT (Continue-to-Interrupt Mode) is not Set Yes Yes Yes Yes

ADC: ADC Offset Trim in Different Modes Yes Yes Yes Yes

ADC: DMA Read of Stale Result Yes Yes Yes Yes

ADC: Random Conversion Errors Yes Yes Yes

ADC: ADC PPB Event Trigger (ADCxEVT) to ePWM Digital Compare Submodule Yes Yes Yes

ADC: 12-Bit Switch Resistance Yes Yes Yes

ADC: 12-Bit Input Capacitance When Switching Channel Groups Yes Yes Yes

ADC: Functionality of VREFLO Pins Yes Yes

ADC: Sensitivity to ESD Events Yes Yes

ADC: ADC Input Multiplexer Connection at Beginning of Acquisition Window Yes Yes

ADC: ADC Sparkle Codes Yes Yes

ADC: ADC Linearity Performance Yes

XRS may Toggle During Power Up Yes Yes Yes

USB: USB DMA Event Triggers are not Supported Yes Yes Yes Yes

VREG: VREG Will be Enabled During Power Up Irrespective of VREGENZ Yes Yes Yes

Flash: A Single-Bit ECC Error May Cause Endless Calls to Single-Bit-Error ISR Yes Yes Yes Yes

Flash: Minimum Programming Word Size Yes Yes Yes Yes

Flash: Reset of CPU2 While it has Pump Ownership Can Cause Erroneous Flash

Reads From CPU1 Yes Yes

ePIE: Spurious VCU Interrupt (ePIE 12.6) Can Occur When First Enabled Yes Yes Yes

eQEP: Position Counter Incorrectly Reset on Direction Change During Index Yes Yes Yes Yes

eQEP: eQEP Inputs in GPIO Asynchronous Mode Yes Yes Yes Yes

PLL: May Not Lock On the First Lock Attempt Yes Yes Yes Yes

PLL: Power Down and Bypass May Take up to 120 SYSCLK Cycles to be Effective Yes Yes Yes Yes

SDFM: Data Filter Output Does Not Saturate at Maximum Value With Sinc3 and

OSR = 256 Yes Yes Yes Yes

SDFM: Spurious Data Acknowledge Event When Data Filter is Configured and

Enabled for the First Time Yes Yes Yes Yes

SDFM: Spurious Data Acknowledge Event When Data Filter is Synchronized Using

PWM FILRES Signal Yes Yes Yes Yes

SDFM: Comparator Filter Module may Generate Spurious Over-Value and Under-

Value Conditions Yes Yes Yes Yes

SDFM: Dynamically Changing Threshold Settings (LLT, HLT), Filter Type, or

COSR Settings Will Trigger Spurious Comparator Events Yes Yes Yes Yes

SDFM: Dynamically Changing Data Filter Settings (Such as Filter Type or DOSR)

Will Trigger Spurious Data Acknowledge Events Yes Yes Yes Yes

FPU: FPU-to-CPU Register Move Operation Preceded by Any FPU 2p Operation Yes Yes Yes Yes

FPU: LUF, LVF Flags are Invalid for the EINVF32 and EISQRTF32 Instructions Yes Yes Yes Yes

Memory: Prefetching Beyond Valid Memory Yes Yes Yes Yes

INTOSC: VDDOSC Powered Without VDD Can Cause INTOSC Frequency Drift Yes Yes Yes Yes

Low-Power Modes: Power Down Flash or Maintain Minimum Device Activity Yes Yes Yes Yes

I2C: SDA and SCL Open-Drain Output Buffer Issue Yes Yes Yes Yes

Usage Notes and Known Design Exceptions to Functional Specifications

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Table 3. List of Advisories (continued)

TITLE SILICON REVISION(S) AFFECTED

0 A B C

ePWM: An ePWM Glitch can Occur if a Trip Remains Active at the End of the

Blanking Window Yes Yes Yes Yes

ePWM: ePWM Dead-Band Delay Value Cannot be Set to 0 When Using Shadow

Load Mode for RED/FED Yes Yes Yes Yes

SYSTEM: Multiple Successive Writes to CLKSRCCTL1 Can Cause a System Hang Yes Yes Yes Yes

CMPSS: COMPxLATCH May Not Clear Properly Under Certain Conditions Yes Yes Yes Yes

CMPSS: Ramp Generator May Not Start Under Certain Conditions Yes Yes Yes Yes

CMPSS: CMPIN4N, CMPIN4P, CMPIN5N, and CMPIN5P Not Available Yes Yes

GPIO: Open-Drain Configuration May Drive a Short High Pulse Yes Yes Yes Yes

GPIO: GPIO0–GPIO7, GPIO46, GPIO47 Shunt to VSS Due to Fast Transients at

High Temperature Yes Yes

During DCAN FIFO Mode, Received Messages May be Placed Out of Order in the

FIFO Buffer Yes Yes Yes Yes

Boot ROM: Calling SCI Bootloader from Application Yes Yes Yes Yes

Boot ROM: Using CPU1 Wait Boot or CPU2 Idle Mode Yes Yes Yes Yes

Boot ROM: Device Will Hang During Boot if X1 Clock Source is not Present Yes

HRPWM: HRCNFG Register Reads and Bit-Wise Writes Yes Yes

SYSBIOS in ROM References Different Flash Sector (Changed From Sector A to

Sector B) Yes Yes

McBSP: McBSP Transmit in SPI Slave Mode Yes Yes

Crystal: Maximum Equivalent Series Resistance (ESR) Values are Reduced Yes Yes

Table 4. Table of Contents for Advisories

Title ...................................................................................................................................... Page

Advisory —Analog Bandgap References............................................................................................. 8

Advisory —Analog Trim of Some TMX Devices ..................................................................................... 9

Advisory —ADC: ADC Post-Processing Block Limit Compare................................................................... 10

Advisory —ADC: Interrupts may Stop if INTxCONT (Continue-to-Interrupt Mode) is not Set ............................... 10

Advisory —ADC: ADC Offset Trim in Different Modes............................................................................ 11

Advisory —ADC: DMA Read of Stale Result....................................................................................... 11

Advisory —ADC: Random Conversion Errors...................................................................................... 12

Advisory —ADC: ADC PPB Event Trigger (ADCxEVT) to ePWM Digital Compare Submodule ............................ 12

Advisory —ADC: 12-Bit Switch Resistance ........................................................................................ 12

Advisory —ADC: 12-Bit Input Capacitance When Switching Channel Groups ................................................ 13

Advisory —ADC: Functionality of VREFLO Pins....................................................................................... 13

Advisory —ADC: Sensitivity to ESD Events ....................................................................................... 13

Advisory —ADC: ADC Input Multiplexer Connection at Beginning of Acquisition Window................................... 14

Advisory —ADC: ADC Sparkle Codes............................................................................................... 15

Advisory —ADC: ADC Linearity Performance...................................................................................... 15

Advisory —XRS may Toggle During Power Up .................................................................................... 16

Advisory —USB: USB DMA Event Triggers are not Supported.................................................................. 16

Advisory —VREG: VREG Will be Enabled During Power Up Irrespective of VREGENZ .................................... 16

Advisory —Flash: A Single-Bit ECC Error May Cause Endless Calls to Single-Bit-Error ISR ............................... 17

Advisory —Flash: Minimum Programming Word Size............................................................................. 17

Advisory —Flash: Reset of CPU2 While it has Pump Ownership Can Cause Erroneous Flash Reads From CPU1..... 18

Advisory —ePIE: Spurious VCU Interrupt (ePIE 12.6) Can Occur When First Enabled...................................... 19

Advisory —eQEP: Position Counter Incorrectly Reset on Direction Change During Index .................................. 20

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Usage Notes and Known Design Exceptions to Functional Specifications

SPRZ412K–December 2013–Revised February 2020

TMS320F2837xD Dual-Core MCUs Silicon Revisions C, B, A, 0

Table 4. Table of Contents for Advisories (continued)

Advisory —eQEP: eQEP Inputs in GPIO Asynchronous Mode.................................................................. 20

Advisory —PLL: May Not Lock on the First Lock Attempt........................................................................ 21

Advisory —PLL: Power Down and Bypass May Take up to 120 SYSCLK Cycles to be Effective .......................... 22

Advisory —SDFM: Data Filter Output Does Not Saturate at Maximum Value With Sinc3 and OSR = 256................ 23

Advisory —SDFM: Spurious Data Acknowledge Event When Data Filter is Configured and Enabled for the First Time 23

Advisory —SDFM: Spurious Data Acknowledge Event When Data Filter is Synchronized Using PWM FILRES Signal 23

Advisory —SDFM: Comparator Filter Module may Generate Spurious Over-Value and Under-Value Conditions ....... 24

Advisory —SDFM: Dynamically Changing Threshold Settings (LLT, HLT), Filter Type, or COSR Settings Will Trigger

Spurious Comparator Events................................................................................................. 24

Advisory —SDFM: Dynamically Changing Data Filter Settings (Such as Filter Type or DOSR) Will Trigger Spurious

Data Acknowledge Events.................................................................................................... 25

Advisory —FPU: FPU-to-CPU Register Move Operation Preceded by Any FPU 2p Operation............................. 26

Advisory —FPU: LUF, LVF Flags are Invalid for the EINVF32 and EISQRTF32 Instructions ............................... 29

Advisory —Memory: Prefetching Beyond Valid Memory ......................................................................... 32

Advisory —INTOSC: VDDOSC Powered Without VDD Can Cause INTOSC Frequency Drift .................................... 32

Advisory —Low-Power Modes: Power Down Flash or Maintain Minimum Device Activity................................... 33

Advisory —I2C: SDA and SCL Open-Drain Output Buffer Issue ................................................................ 34

Advisory — ePWM: An ePWM Glitch can Occur if a Trip Remains Active at the End of the Blanking Window........... 36

Advisory —ePWM: ePWM Dead-Band Delay Value Cannot be Set to 0 When Using Shadow Load Mode for

RED/FED........................................................................................................................ 36

Advisory —SYSTEM: Multiple Successive Writes to CLKSRCCTL1 Can Cause a System Hang.......................... 37

Advisory —CMPSS: COMPxLATCH May Not Clear Properly Under Certain Conditions .................................... 38

Advisory —CMPSS: Ramp Generator May Not Start Under Certain Conditions .............................................. 38

Advisory —CMPSS: CMPIN4N, CMPIN4P, CMPIN5N, and CMPIN5P Not Available........................................ 38

Advisory —GPIO: Open-Drain Configuration May Drive a Short High Pulse .................................................. 39

Advisory —GPIO: GPIO0–GPIO7, GPIO46, GPIO47 Shunt to VSS Due to Fast Transients at High Temperature........ 40

Advisory —During DCAN FIFO Mode, Received Messages May be Placed Out of Order in the FIFO Buffer ............ 41

Advisory —Boot ROM: Calling SCI Bootloader from Application ................................................................ 42

Advisory —Boot ROM: Using CPU1 Wait Boot or CPU2 Idle Mode ............................................................ 42

Advisory —Boot ROM: Device Will Hang During Boot if X1 Clock Source is not Present ................................... 42

Advisory —HRPWM: HRCNFG Register Reads and Bit-Wise Writes .......................................................... 43

Advisory —SYSBIOS in ROM References Different Flash Sector (Changed From Sector A to Sector B) ................ 43

Advisory —McBSP: McBSP Transmit in SPI Slave Mode........................................................................ 43

Advisory —Crystal: Maximum Equivalent Series Resistance (ESR) Values are Reduced................................... 44

Usage Notes and Known Design Exceptions to Functional Specifications

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TMS320F2837xD Dual-Core MCUs Silicon Revisions C, B, A, 0

Advisory Analog Bandgap References

Revision(s) Affected 0, A, B, C

Details The Analog Subsystem includes internal bandgap reference circuits that are shared by

the embedded analog modules. Table 5 shows the bandgap usage by module.

Table 5. Bandgap Usage by Module

BANDGAP ADC BUFFERED DAC CMPSS

BGA ADCA DACA

DACB CMPSS1

CMPSS2

BGB ADCB DACC CMPSS3

CMPSS4

BGC ADCC CMPSS5

CMPSS6

BGD ADCD CMPSS7

CMPSS8

Each bandgap reference—BGA, BGB, BGC, or BGD—will power up when one or more

of the dependent modules are enabled. An active bandgap reference will power down if

all dependent modules are disabled.

For example, bandgap B (BGB) is powered down unless one or more of the following

• AdcbRegs.ADCCTL1.bit.ADCPWDNZ

• DaccRegs.DACOUTEN.bit.DACOUTEN

• Cmpss3Regs.COMPCTL.bit.COMPDACE

• Cmpss4Regs.COMPCTL.bit.COMPDACE

The CMPSS and GPDAC power-up time specification in the TMS320F2837xD Dual-

Core Microcontrollers Data Manual previously did not account for the bandgap power-up

time. This 10-µs value has been increased to 500 µs to account for the bandgap power-

up time.

Workaround(s) If your application was utilizing a power-up time of 10 µs for the CMPSS and GPDAC,

you do not need to increase it to 500 µs if the respective ADC on that bandgap was

turned on before the CMPSS and GPDAC, and the ADC power-up time of 500 µs was

adhered to.

For simplicity, it is recommended that 500 µs be used as the power-up time for both

CMPSS and GPDAC.

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SPRZ412K–December 2013–Revised February 2020

TMS320F2837xD Dual-Core MCUs Silicon Revisions C, B, A, 0

Advisory Analog Trim of Some TMX Devices

Revision(s) Affected 0, A, B

Details Some TMX samples may not have analog trims programmed. This could degrade the

performance of the ADC, buffered DAC, and internal oscillators. A value of all zeros in

these trim registers due to lack of trim will have the following impact.

TRIM REGISTER IMPACT OF UNTRIMMED REGISTER

ADC reference AnalogSubsysRegs.ANAREFTRIMA Degraded performance of the ADC for all

specifications.

AnalogSubsysRegs.ANAREFTRIMB

AnalogSubsysRegs.ANAREFTRIMC

AnalogSubsysRegs.ANAREFTRIMD

ADC linearity AdcaRegs.ADCINLTRIM1-6 Degraded INL and DNL specifications of the ADC

in 16-bit mode. No workaround available.

AdcbRegs.ADCINLTRIM1-6

AdccRegs.ADCINLTRIM1-6

AdcdRegs.ADCINLTRIM1-6

ADC offset AdcaRegs.ADCOFFTRIM Degraded performance of the ADC offset error

specification.

AdcbRegs.ADCOFFTRIM

AdccRegs.ADCOFFTRIM

AdcdRegs.ADCOFFTRIM

Internal oscillator AnalogSubsysRegs.INTOSC1TRIM Degraded frequency accuracy and temperature

drift of the internal oscillators.

AnalogSubsysRegs.INTOSC2TRIM

Buffered DAC offset DacaRegs.DACTRIM Degraded offset error specification of the buffered

DAC. No workaround available.

DacbRegs.DACTRIM

DaccRegs.DACTRIM

Workaround(s) The following workarounds can be used for improved performance, though it still may not

meet data sheet specifications.

To determine if a device is TMX in software, check the status of the PARTIDL[QUAL]. If

this field is 0, the device is TMX. PARTIDL[QUAL] can be read via the function call

SysCtl_getDeviceParametric(SYSCTL_DEVICE_QUAL). This check is implemented in

the Device_init() function, which will then call the Device_configureTMXAnalogTrim()

function if needed. The user can place any additional self-calibration or static calibration

code in the Device_configureTMXAnalogTrim() function.

If the ADC reference trim registers contain all zeros, write the static reference trim value

of 0x7BDD to the reference trim register for all ADCs.

Missing ADC offset trim can be generated by following the instructions in the “ADC

Zero Offset Calibration” section of the TMS320F2837xD Dual-Core Microcontrollers

Technical Reference Manual.

If the internal oscillator trim contains all zeros, the user can adjust the lowest 10 bits of

the oscillator trim register between 1 (minimum) and 1023 (maximum) while observing

the system clock on the XCLOCKOUT pin.

Usage Notes and Known Design Exceptions to Functional Specifications

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Advisory ADC: ADC Post-Processing Block Limit Compare

Revision(s) Affected 0, A, B, C

Details When using a non-zero offset reference in the ADC post-processing block (PPB), the

resultant ADCPPBxRESULT can be signed. TRIPHI or TRIPLO limit compares do not

function correctly with this result if it is signed.

Workaround(s) When using the TRIPHI or TRIPLO limit compares, leave the offset reference as zero.

The offset reference (and zero compare) can be used as long as the limit compares are

disabled.

If the limit compares, the offset reference, and the zero-crossing compare are to be used

at the same time, then two PPBs can be used. Both PPBs should be configured to use

the same SOC. One PPB can implement the TRIPHI and/or TRIPLO limit compares

while the other can implement offset reference subtraction and zero-crossing detection.

Advisory ADC: Interrupts may Stop if INTxCONT (Continue-to-Interrupt Mode) is not Set

Revision(s) Affected 0, A, B, C

Details If ADCINTSELxNx[INTxCONT] = 0, then interrupts will stop when the ADCINTFLG is set

and no additional ADC interrupts will occur.

When an ADC interrupt occurs simultaneously with a software write of the

ADCINTFLGCLR register, the ADCINTFLG will unexpectedly remain set, blocking future

ADC interrupts.

Workaround(s) 1. Use Continue-to-Interrupt Mode to prevent the ADCINTFLG from blocking additional

ADC interrupts:

ADCINTSEL1N2[INT1CONT] = 1;

ADCINTSEL1N2[INT2CONT] = 1;

ADCINTSEL3N4[INT3CONT] = 1;

ADCINTSEL3N4[INT4CONT] = 1;

2. Ensure there is always sufficient time to service the ADC ISR and clear the

ADCINTFLG before the next ADC interrupt occurs to avoid this condition.

3. Check for an overflow condition in the ISR when clearing the ADCINTFLG. Check

ADCINTOVF immediately after writing to ADCINTFLGCLR; if it is set, then write

ADCINTFLGCLR a second time to ensure the ADCINTFLG is cleared. The

ADCINTOVF register will be set, indicating an ADC conversion interrupt was lost.

AdcaRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; //clear INT1 flag

if(1 == AdcaRegs.ADCINTOVF.bit.ADCINT1) //ADCINT overflow

{AdcaRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; //clear INT1 again

// If the ADCINTOVF condition will be ignored by the application

// then clear the flag here by writing 1 to ADCINTOVFCLR.

// If there is a ADCINTOVF handling routine, then either insert

// that code and clear the ADCINTOVF flag here or do not clear

// the ADCINTOVF here so the external routine will detect the

// condition.

// AdcaRegs.ADCINTOVFCLR.bit.ADCINT1 = 1; // clear OVF

}

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