Texas Instruments DS90UB913Q Manual de usuario

DS90UB913Q/DS90UB914Q

10-100MHz 10/12- Bit DC-Balanced FPD-Link III Serializer and

Deserializer with Bidirectional Control Channel

General Description

The DS90UB913Q/DS90UB914Q chipset offers a FPD-Link

III interface with a high-speed forward channel and a bidirec-

tional control channel for data transmission over a single

differential pair. The DS90UB913Q/914Q chipsets incorpo-

rate differential signaling on both the high-speed forward

channel and bidirectional control channel data paths. The Se-

rializer/ Deserializer pair is targeted for connections between

imagers and video processors in an ECU (Electronic Control

Unit). This chipset is ideally suited for driving video data re-

quiring up to 12 bit pixel depth plus two synchronization

signals along with bidirectional control channel bus.

There is a multiplexer at the Deserializer to choose between

two input imagers. The Deserializer can have only one active

input imager. The primary video transport converts 10/12 bit

data over a single high-speed serial stream, along with a sep-

arate low latency bidirectional control channel transport that

accepts control information from an I2C port and is indepen-

dent of video blanking period.

Using TI’s embedded clock technology allows transparent full-

duplex communication over a single differential pair, carrying

asymmetrical bidirectional control channel information in both

directions. This single serial stream simplifies transferring a

wide data bus over PCB traces and cable by eliminating the

skew problems between parallel data and clock paths. This

significantly saves system cost by narrowing data paths that

in turn reduce PCB layers, cable width, and connector size

and pins. In addition, the Deserializer inputs provide adaptive

equalization to compensate for loss from the media over

longer distances. Internal DC balanced encoding/decoding is

used to support AC-Coupled interconnects. The Serializer is

offered in a 32-pin LLP package and the Deserializer is of-

fered in a 48-pin LLP package.

Features

●10 MHz to 100 MHz input pixel clock support

●Single differential pair interconnect

●Programmable data payload:

—10 bit payload up to 100Mhz

—12 bit payload up to 75MHz

●Continuous Low Latency Bidirectional control interface

channel with I2C support@400kHz

●2:1 Multiplexer to choose between two input imagers

●Embedded clock with DC Balanced coding to support AC-

coupled interconnects

●Capable of driving up to 25 meters shielded twisted-pair

●Receive Equalizer automatically adapts for changes in

cable loss

●4 dedicated General Purpose Input (GPI)/ Output (GPO)

●LOCK output reporting pin and AT-SPEED BIST diagnosis

feature to validate link integrity

●1.8V, 2.8V or 3.3V compatible parallel inputs on Serializer

●Single power supply at 1.8V

●ISO 10605 and IEC 61000-4-2 ESD Compliant

●Automotive grade product: AEC-Q100 Grade 2 qualified

●Temperature range −40°C to +105°C

●Small serializer footprint (5mm x 5mm)

●EMI/EMC Mitigation - Deserializer

—Programmable Spread Spectrum (SSCG) outputs.

—Receiver staggered outputs

Applications

●Front or rear view camera for collision mitigation

●Surround view for parking assistance

Typical Application Diagram

30144627

FIGURE 1. Typical Application Circuit

TRI-STATE® is a registered trademark of National Semiconductor Corporation.

PRODUCTION DATA information is current as of

publication date. Products conform to specifications per

the terms of the Texas Instruments standard warranty.

Production processing does not necessarily include

testing of all parameters.

Block Diagrams

30144628

FIGURE 2. Block Diagram

30144629

FIGURE 3. Application Block Diagram

DS90UB913Q/DS90UB914Q

Ordering Information

NSID Package Description Quantity SPEC Package ID

DS90UB913QSQE 32-pin LLP, 5.0 X 5.0 X 0.8 mm, 0.5 mm pitch 250 NOPB SQA32A

DS90UB913QSQ 32-pin LLP, 5.0 X 5.0 X 0.8 mm, 0.5 mm pitch 1000 NOPB SQA32A

DS90UB913QSQX 32-pin LLP, 5.0 X 5.0 X 0.8 mm, 0.5 mm pitch 2500 NOPB SQA32A

DS90UB914QSQE 48-pin LLP, 7.0 X 7.0 X 0.8 mm, 0.5 mm pitch 250 NOPB SQA48A

DS90UB914QSQ 48-pin LLP, 7.0 X 7.0 X 0.8 mm, 0.5 mm pitch 1000 NOPB SQA48A

DS90UB914QSQX 48-pin LLP, 7.0 X 7.0 X 0.8 mm, 0.5 mm pitch 2500 NOPB SQA48A

DS90UB913Q Pin Diagram

30144619

Serializer - DS90UB913Q — Top View

DS90UB913Q Serializer Pin Descriptions

Pin Name Pin No. I/O, Type Description

LVCMOS PARALLEL INTERFACE

DIN[0:11] 19,20,21,22,

23,24,26,27,

29,30,31,32

Inputs, LVCMOS

w/ pull down

Parallel Data Inputs.

HSYNC 1 Inputs, LVCMOS

w/ pull down

Horizontal SYNC Input

VSYNC 2 Inputs, LVCMOS

w/ pull down

Vertical SYNC Input

PCLK 3 Input, LVCMOS

w/ pull down

Pixel Clock Input Pin. Strobe edge set by TRFB control register.

GENERAL PURPOSE OUTPUT (GPO)

DS90UB913Q/DS90UB914Q

Pin Name Pin No. I/O, Type Description

GPO[1:0] 16,15 Output,

LVCMOS

General-purpose output pins can be configured as outputs; used to control and

respond to various commands. GPO[0:1] can be configured to be the outputs for

input signals coming from GPIO[0:1] pins on the Deserializer or can be configured

to be outputs of the local register on the Serializer.

GPO[2]/

CLKOUT

17 Output,

LVCMOS

GPO2 pin can be configured to be the output for input signal coming from the GPIO2

pin on the Deserializer or can be configured to be the output of the local register on

the Serializer. It can also be configured to be the output clock pin when the

DS90UB913Q device is used in the External Oscillator mode. See Applications

Information for a detailed description of the DS90UB913/914Q chipsets working

with the external oscillator.

GPO[3]/CLKIN 18 Input/Output,

LVCMOS

GPO3 can be configured to be the output for input signals coming from the GPIO3

pin on the Deserializer or can be configured to be the output of the local register

setting on the Serializer. It can also be configured to be the input clock pin when

the DS90UB913Q Serializer is working with an external oscillator. See Applications

Information section for a detailed description of the DS90UB913/914Q chipsets

working with an external oscillator.

BIDIRECTIONAL CONTROL BUS - I2C COMPATIBLE

SCL 4 Input/Output,

Open Drain

Clock line for the bidirectional control bus communication

SCL requires an external pull-up resistor to VDDIO.

SDA 5 Input/Output,

Open Drain

Data line for the bidirectional control bus communication

SDA requires an external pull-up resistor to VDDIO.

MODE 8 Input, LVCMOS

w/ pull down

Device mode select

Resistor to Ground and 10 kΩpull-up to 1.8V rail. MODE pin on the Serializer can

be used to select whether the system is running off the PCLK from the imager or

an external oscillator. See details in Table 5

ID[x] 6 Input, analog

Device ID Address Select

The ID[x] pin on the Serializer is used to assign the I2C device address. Resistor

to Ground and 10 kΩpull-up to 1.8V rail. See Table 7

CONTROL AND CONFIGURATION

PDB 9 Input, LVCMOS

w/ pull down

Power down Mode Input Pin.

PDB = H, Serializer is enabled and is ON.

PDB = L, Serailizer is in Power Down mode. When the Serializer is in Power Down,

the PLL is shutdown, and IDD is minimized. Programmed control register data are

NOT retained and reset to default values

RES 7 Input, LVCMOS

w/ pull down

Reserved.

This pin MUST be tied LOW.

FPD–Link III INTERFACE

DOUT+ 13 Input/Output,

CML

Non-inverting differential output, bidirectional control channel input. The

interconnect must be AC Coupled with a 100 nF capacitor.

DOUT- 12 Input/Output,

CML

Inverting differential output, bidirectional control channel input. The interconnect

must be AC Coupled with a 100 nF capacitor.

POWER AND GROUND

VDDPLL 10 Power, Analog PLL Power, 1.8V ±5%

VDDT 11 Power, Analog Tx Analog Power, 1.8V ±5%

VDDCML 14 Power, Analog CML & Bidirectional Channel Driver Power, 1.8V ±5%

VDDD 28 Power, Digital Digital Power, 1.8V ±5%

VDDIO 25 Power, Digital Power for I/O stage. The single-ended inputs and SDA, SCL are powered from

VDDIO. VDDIO can be connected to a 1.8V ±5% or 2.8±10% or 3.3V ±10%

VSS DAP

Ground, DAP DAP must be grounded. DAP is the large metal contact at the bottom side, located

at the center of the LLP package. Connected to the ground plane (GND) with at

least 9 vias.

DS90UB913Q/DS90UB914Q

DS90UB914Q Pin Diagram

30144620

Deserializer - DS90UB914Q — Top View

DS90UB914Q Deserializer Pin Descriptions

Pin Name Pin No. I/O, Type Description

LVCMOS PARALLEL INTERFACE

ROUT[11:0] 11,12,13,14,

15,16,18,19,

21,22,23,24

Outputs,

LVCMOS

Parallel Data Outputs.

HSYNC 10 Output,

LVCMOS

Horizontal SYNC Output.

VSYNC 9 Output,

LVCMOS

Vertical SYNC Output.

PCLK 8 Output,

LVCMOS

Pixel Clock Output Pin.

Strobe edge set by RRFB control register.

GENERAL PURPOSE INPUT/OUTPUT (GPIO)

GPI0[1:0] 27,28

Digital Input/

Output,

LVCMOS

General-purpose input/output pins can be used to control and respond to various

commands. They may be configured to be the input signals for the corresponding

GPOs on the serializer or they may be configured to be outputs to follow local

GPIO[3:2] 25,26 Digital Input/

Output LVCMOS

General purpose input/output pins GPO[2:3] can be configured to be input signals

for GPOs on the Serializer. In addition they can also be configured to be outputs to

follow the local register settings. When the SerDes chipsets are working with an

external oscillator, these pins can be configured only to be outputs to follow the local

BIDIRECTIONAL CONTROL BUS - I2C COMPATIBLE

SCL 2 Input/Output,

Open Drain

Clock line for the bidirectional control bus communication

SCL requires an external pull-up resistor to VDDIO.

SDA 1 Input/Output,

Open Drain

Data line for bidirectional control bus communication

SDA requires an external pull-up resistor to VDDIO.

DS90UB913Q/DS90UB914Q

Pin Name Pin No. I/O, Type Description

MODE 37 Input, LVCMOS

w/ pull up

Device mode select pin

Resistor to Ground and 10 kΩpull-up to 1.8V rail. The MODE pin on the Deserializer

can be used to configure the Serializer and Deserializer to work in different input

PCLK range. See details in Table 2.

12– bit low frequency mode – (10- 50 MHz operation):

In this mode, the Serializer and Deserializer can accept up to 12 bits DATA+2

SYNC. Input PCLK range is from 10MHz to 50MHz.

12– bit high frequency mode – (15-75 MHz operation): In this mode, the

Serializer and Deserializer can accept up to 12 bits DATA + 2 SYNC. Input PCLK

range is from 15MHz to 75MHz.

10–bit mode– (20–100 MHz operation):

In this mode, the Serializer and Deserializer can accept up to 10 bits DATA + 2

SYNC. Input PCLK frequency can range from20 MHz to 100MHz.

Please refer to Table 6 in the Applications Information section on how to configure

the MODE pin on the Deserializer.

IDx[0:1] 35,34 Input, analog The IDx[0] and IDx[1] pins on the Deserializer are used to assign the I2C device

address. Resistor to Ground and 10 kΩpull-up to 1.8V rail. See Table 8

CONTROL AND CONFIGURATION

PDB 30 Input, LVCMOS

w/ pull down

Power down Mode Input Pin.

PDB = H, Deserializer is enabled and is ON.

PDB = L, Deserializer is in Sleep (power down mode). When the Deserializer is in

Sleep, programmed control register data are NOT retained and reset to default

values.

LOCK 48 Output,

LVCMOS

LOCK Status Output Pin.

LOCK = H, PLL is Locked, outputs are active

LOCK = L, PLL is unlocked, ROUT and PCLK output states are controlled by

OSS_SEL control register. May be used as Link Status.

BISTEN 6

Input

LVCMOS w/

pulldown

BIST Enable pin

BISTEN=H, BIST Mode Enabled

BISTEN=L, BIST Mode is disabled

PASS 47 Output,

LVCOMS

PASS Output Pin for BIST mode.

PASS = H, ERROR FREE Transmission

PASS = L, one or more errors were detected in the received payload.

See BIST section for more information. Leave Open if unused. Route to test point

(pad) recommended.

OEN 5

Input

LVCMOS w/

pulldown

Output Enable Input

Refer to Table 9

OSS_SEL 4

Input

LVCMOS w/

pulldown

Output Sleep State Select Pin

Refer to Table 9

SEL 46

Input

LVCMOS w/

pulldown

MUX Select line

SEL = L, RIN0+/- input. This selects input A as the active channel on the

Deserializer.

SEL = H, RIN1+/- input. This selects input B as the active channel on the

Deserializer.

FPD–Link III INTERFACE

RIN0+ 41 Input/Output,

CML

Non-Inverting Differential input, bidirectional control channel. The IO must be AC

coupled with a 100 nF capacitor

RIN0- 42 Input/Output,

CML

Inverting Differential input, bidirectional control channel. The IO must be AC

coupled with a 100 nF capacitor

RIN1+ 32 Input/Output,

CML

Non-Inverting Differential input, bidirectional control channel. The IO must be AC

coupled with a 100 nF capacitor

RIN1- 33 Input/Output,

CML

Inverting Differential input, bidirectional control channel. The IO must be AC

coupled with a 100 nF capacitor

DS90UB913Q/DS90UB914Q

Pin Name Pin No. I/O, Type Description

RES 43,44 —Reserved. This pin must always be tied low

CMLOUTP/N 38,39 Route to test point or leave open if unused

POWER AND GROUND

VDDIO1/2/3 29, 20, 7 Power, Digital LVCMOS I/O Buffer Power, The single-ended outputs and control input are

powered from VDDIO. VDDIO can be connected to a 1.8V ±5% or 3.3V ±10%

VDDD 17 Power, Digital Digital Core Power, 1.8V ±5%

VDDSSCG 3 Power, Analog SSCG PLL Power, 1.8V ±5%

VDDR 36 Power, Analog Rx Analog Power, 1.8V ±5%

VDDCML0/1 40,31 Power, Analog CML and Bidirectional control channel Drive Power, 1.8V±5%

VDDPLL 45 Power, Analog PLL Power, 1.8V ±5%

VSS DAP Ground, DAP

DAP must be grounded. DAP is the large metal contact at the bottom side, located

at the center of the LLP package. Connected to the ground plane (GND) with at

least 16 vias.

DS90UB913Q/DS90UB914Q

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for

availability and specifications.

Supply Voltage – VDDn (1.8V) −0.3V to +2.5V

Supply Voltage – VDDIO −0.3V to +4.0V

LVCMOS Input Voltage I/O

Voltage −0.3V to + (VDDIO + 0.3V)

CML Driver I/O Voltage (VDD) −0.3V to +(VDD + 0.3V)

CML Receiver I/O Voltage

(VDD) −0.3V to (VDD + 0.3V)

Junction Temperature +150°C

Storage Temperature −65°C to +150°C

Maximum Package Power

Dissipation Capacity Package 1/θJA °C/W above +25°

Package Derating:

DS90UB913Q 32L LLP

θJA

(based on 16 thermal vias)

38.4 °C/W

θJC

(based on 16 thermal vias)

6.9 °C/W

DS90UB914Q 48L LLP

θJA

(based on 16 thermal vias)

26.9 °C/W

θJC

(based on 16 thermal vias)

4.4 °C/W

ESD Rating (IEC 61000-4-2) RD = 330Ω, CS= 150pF

Air Discharge

(DOUT+, DOUT-, RIN+, RIN-) ≥±25 kV

Contact Discharge

(DOUT+, DOUT-, RIN+, RIN-) ≥±7 kV

ESD Rating (ISO10605) RD = 330Ω, CS= 150/330pF

ESD Rating (ISO10605) RD= 2KΩ, CS= 150/330pF

Air Discharge

(DOUT+, DOUT-, RIN+, RIN-) ≥±15 kV

Contact Discharge

(DOUT+, DOUT-, RIN+, RIN-) ≥±8 kV

ESD Rating (HBM) ≥±8 kV

ESD Rating (CDM) ≥±1 kV

ESD Rating (MM) ≥±250 V

For soldering specifications:

see product folder at www.ti.com and

www.ti.com/lit/an/snoa549c/snoa549c.pdf

Recommended Operating Conditions

Min Nom Max Units

Supply Voltage

(VDDn)

1.71 1.8 1.89 V

LVCMOS Supply

Voltage (VDDIO)

1.71 1.8 1.89 V

LVCMOS Supply

Voltage (VDDIO)

3.0 3.3 3.6 V

LVCMOS Supply

Voltage (VDDIO)

Only Serializer

2.52 2.8 3.08 V

Supply Noise

DS90UB913Q/DS90UB914Q

Min Nom Max Units

VDDn (1.8V) 25 mVp-p

VDDIO (1.8V) 25 mVp-p

VDDIO (3.3V) 50 mVp-p

Operating Free Air

Temperature (TA)-40 +25 +105 °C

PCLK Clock

Frequency

10 100 MHz

Electrical Characteristics (Note 2, Note 3, Note 4)

Over recommended operating supply and temperature ranges unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Units

LVCMOS DC SPECIFICATIONS 3.3V I/O (SER INPUTS, DES OUTPUTS, GPI, GPO, CONTROL INPUTS AND OUTPUTS)

VIH High Level Input Voltage VIN = 3.0V to 3.6V 2.0 VIN V

VIL Low Level Input Voltage VIN = 3.0V to 3.6V GND 0.8 V

IIN Input Current VIN = 0V or 3.6V

VIN = 3.0V to 3.6V -20 ±1 +20 µA

VOH High Level Output Voltage VDDIO = 3.0V to 3.6V

IOH = −4 mA 2.4 VDDIO V

VOL Low Level Output Voltage VDDIO = 3.0V to 3.6V

IOL = +4 mA GND 0.4 V

IOS Output Short Circuit Current VOUT = 0V Serializer

GPO Outputs -15

Deserializer

LVCMOS Outputs -35

IOZ TRI-STATE® Output Current PDB = 0V,

VOUT = 0V or VDD

LVCMOS Outputs -20 +20 µA

LVCMOS DC SPECIFICATIONS 1.8V I/O (SER INPUTS, DES OUTPUTS, GPI, GPO, CONTROL INPUTS AND OUTPUTS)

VIH High Level Input Voltage VIN = 1.71V to 1.89V 0.65 VIN VIN V

VIL Low Level Input Voltage VIN = 1.71V to 1.89V GND 0.35 VIN

IIN Input Current VIN = 0V or 1.89V

VIN = 1.71V to 1.89V -20 ±1 +20 µA

VOH High Level Output Voltage VDDIO = 1.71V to 1.89V

IOH = −4 mA

VDDIO -

0.45 VDDIO V

VOL Low Level Output Voltage VDDIO = 1.71V to 1.89V

IOL = +4 mA

Deserializer

LVCMOS Outputs GND 0.45 V

IOS Output Short Circuit Current VOUT = 0V Serializer

GPO Outputs -11

Deserializer

LVCMOS Outputs -17

IOZ TRI-STATE® Output Current PDB = 0V,

VOUT = 0V or VDD

LVCMOS Outputs -20 +20 µA

LVCMOS DC SPECIFICATIONS 2.8V I/O (SER INPUTS, GPI, GPO, CONTROL INPUTS AND OUTPUTS)

VIH High Level Input Voltage VIN = 2.52V to 3.08V 0.7 VIN VIN V

VIL Low Level Input Voltage VIN = 2.52V to 3.08V GND 0.3 VIN

IIN Input Current VIN = 0V or 3.08V

VIN = 2.52V to 3.08V -20 ±1 +20 µA

VOH High Level Output Voltage VDDIO = 2.52V to 3.08V

IOH = −4 mA VDDIO - 0.4 VDDIO V

VOL Low Level Output Voltage VDDIO =2.52V to 3.08V

IOL = +4 mA

Deserializer

LVCMOS Outputs GND 0.4 V

DS90UB913Q/DS90UB914Q

Symbol Parameter Conditions Min Typ Max Units

IOS Output Short Circuit Current VOUT = 0V Serializer

GPO Outputs -11

Deserializer

LVCMOS Outputs -20

IOZ TRI-STATE® Output Current PDB = 0V,

VOUT = 0V or VDD

LVCMOS Outputs -20 +20 µA

CML DRIVER DC SPECIFICATIONS (DOUT+, DOUT-)

|VOD|Output Differential Voltage RL = 100Ω (Figure 7)268 340 412 mV

ΔVOD

Output Differential Voltage

Unbalance

RL = 100Ω 1 50 mV

VOS Output Differential Offset

Voltage

RL = 100Ω

(Figure 7)VDD - VOD/2 V

ΔVOS Offset Voltage Unbalance RL = 100Ω 1 50 mV

IOS Output Short Circuit Current DOUT+/- = 0V -26 mA

RTDifferential Internal

Termination Resistance

Differential across DOUT+ and DOUT- 80 100 120 Ω

CML RECEIVER DC SPECIFICATIONS (RIN0+,RIN0–,RIN1+,RIN1– )

IIN

Input Current VIN = VDD or 0V,

VDD = 1.89V -20 1 +20 µA

RTDifferential Internal

Termination Resistance

Differential across RIN+ and RIN- 80 100 120 Ω

CML RECEIVER AC SPECIFICATIONS (RIN0+,RIN0–,RIN1+,RIN1– )

|Vswing|Minimum allowable swing for

1010 pattern (Note 10)

Line Rate = 1.4Gbps (Figure 8)135 mV

CMLMONITOR OUTPUT DRIVER SPECIFICATIONS(CMLOUTP, CMLOUTN)

Differntial Output Eye

Opening

RL = 100Ω

Jitter Frequency>f/40 (Figure 17)0.45 UI

EHDifferential Output Eye

Height 200 mV

SER/DES SUPPLY CURRENT *DIGITAL, PLL, AND ANALOG VDD

DS90UB913Q/DS90UB914Q

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