Terasic LT24 Manual de usuario

DE10-Standard

LT24 Display

1 www.terasic.com

March 20, 2017

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This document illustrates how to setup the LT24-Display demo on the DE10-Standard

and the LT24 as shown in Figure 1. The basic design content is also included. In this

demonstration, please refer to the DE10-Standard user manual. For details about the

LT24, please refer to the user manual of LT24 daughter card.

Figure 1 LT24 Painter Demo

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The following items are required to perform this demonstration:

DE10-Standard and power supply

LT24 LCD touch module

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Please follow the procedures below to setup the demonstration:

1. Make sure both Quartus II and USB-Blaster II driver are installed on the host

PC.

2. Power off the DE10-Standard board.

3. Connect a mini-USB cable to an UB2 port of the DE10-Standard and the host

PC.

4. Mount the LT24 onto the 2x20 GPIO (JP1) expansion header of the DE10-

Standard.

5. Power on the DE10-Standard Board.

6. Make sure Quartus Prime 16.0 Standard or later is installed on your host PC.

7. Launch the “test.bat” from the folder demo_batch of the

\DE10_Standard_LT24_Display\demo_batch

8. The RGB-Display demo should be up and running on the LCD.

DE10-Standard

LT24 Display

2 www.terasic.com

March 20, 2017

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Figure 2 shows the system block diagram of LT24-Display demonstration.

LT24_Display of RTL (Verilog) code on the demo project of "/ip/lt24_display" folder.

As shown Figure 2 , lt24_display the top module - lt24_display.v contains four block.

Pat_update.v is used with Touch (AD7843) connection, pat_update module will

receive the AD7843 in touch information (x, y coordinates), and then converted into

the corresponding action, this action triggers to the LCD display module generates

commands, and command again through cmd2lcd module to convert LCD panel

(ILI9341) can accept signals. The last timer module has only one function - to

produce a 33ms signal, which is used to make a long delay of the clock, such as LCD

during the initial stage will need ms dela.

Figure 2 System Block Diagram

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