Supermicro SUPER P6DNH2 Manual de usuario

SUPER

Dual Pentium Pro Processor

SUPER P6DNH

SUPER P6DNH2

USER’S MANUAL

Revision 1.1

The information in this User’s Manual has been carefully reviewed and is believed to be

accurate. The vendor assumes no responsibility for any inaccuracies that may be

contained in this document, makes no commitment to update or to keep current the

information in this manual, or to notify any person or organization of the updates.

SUPERMICRO COMPUTER reserves the right to make changes to the product described in

this manual at any time and without notice. This product, including software, if any, and

documentation may not, in whole or in part, be copied, photocopied, reproduced, translated

or reduced to any medium or machine without prior written consent.

IN NO EVENT WILL SUPERMICRO COMPUTER BE LIABLE FOR DIRECT, INDIRECT,

SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING FROM THE USE OR

INABILITY TO USE THIS PRODUCT OR DOCUMENTATION, EVEN IF ADVISED OF THE

POSSIBILITY OF SUCH DAMAGES. IN PARTICULAR, THE VENDOR SHALL NOT HAVE

LIABILITY FOR ANY HARDWARE, SOFTWARE, OR DATA STORED OR USED WITH THE

PRODUCT, INCLUDING THE COSTS OF THE REPAIRING, REPLACING, OR

RECOVERING SUCH HARDWARE, SOFTWARE, OR DATA.

Unless you request and receive written permission from SUPERMICRO COMPUTER, you

may not copy any part of this document.

Information in this document is subject to change without notice. Other products and

companies referred to herein are trademarks or registered trademarks of their respective

companies or mark holders.

Printed in the United States of America.

iii

Preface

About This Manual

This manual is written for system houses, PC technicians and

knowledgeable PC end users. It provides information for the instal-

lation and use of the SUPER®P6DNH/P6DNH2 motherboard, which

supports the 200/180/166/150, >200 MHz Intel®Pentium® Pro pro-

cessors, and the i960®RP IO processor.

The Pentium Pro processor has two 64-bit data buses. One bus

interconnects to the built-in L2 cache and the other is an external

bus that interconnects with the system memory, I/O and the other

processor. Both come with ECC (Error Checking and Correction)

allowing for the correction of single-bit data errors and detection of

2-bit errors on the data bus.

Manual Organization

Chapter 1, Introduction, describes the features, specifications and

performance of the SUPER P6DNH/P6DNH2 system board, pro-

vides detailed information about the chipset, and offers warranty

information.

Refer to Chapter 2, Installation, for a list of the equipment needed

for a system based on the SUPER P6DNH/P6DNH2 system board.

This chapter provides you with the instructions for handling static-

sensitive devices, checking and/or configuring the jumpers. Read

this chapter when you want to install or remove SIMM memory mod-

ules and to mount the system board in the chassis. Also refer to

this chapter to connect the floppy and hard disk drives, USB, IDE

interface, parallel port, serial ports, as well as the cables for the

power supply, reset cable, Keylock/Power LED, speaker and key-

board.

If you encounter any problem, please see Chapter 3, Troubleshoot-

ing, which describes troubleshooting procedures for video, memo-

ry, and the setup configuration stored in memory. Instructions are

also included on contacting a technical assistance support repre-

sentative and returning merchandise for service and the BBS# for

BIOS upgrades .

SUPER P6DNH/P6DNH2 User's Manual

Preface

Table of Contents

Preface

About This Manual ......................................................................................... iii

Manual Organization...................................................................................... iii

Chapter 1:

1-1 Overview............................................................................................... 1-1

SUPER P6DNH/P6DNH2 Motherboard Layout ...................... 1-4

SUPER P6DNH/P6DNH2 System Board Architecture.......... 1-5

Features......................................................................................... 1-6

1-2 Power Supply ...................................................................................... 1-8

1-3 Chipset Overview................................................................................ 1-8

1-4 National Semiconductor 87306 ....................................................... 1-9

1-5 Voltage Regulator Modules .............................................................. 1-9

1-6 System Overheat Thermal Control ................................................ 1-10

1-7 Warranty, Technical Support, and Service.................................. 1-11

Parts.............................................................................................. 1-11

BIOS .............................................................................................. 1-11

Labor............................................................................................. 1-11

Returns......................................................................................... 1-11

Chapter 2: Installation

2-1 SUPER P6DNH/P6DNH2 System Components.......................... 2-1

Standard System Configuration ................................................ 2-1

Enhanced System Configuration .............................................. 2-2

2-2 Static-Sensitive Devices ................................................................... 2-2

Precautions ................................................................................... 2-2

Unpacking...................................................................................... 2-3

2-3 Configuring System Board Jumpers.............................................. 2-3

Manufacturing Settings ............................................................... 2-3

Changing the CPU Speed ......................................................... 2-4

2-4 Mounting the Motherboard in the Chassis................................... 2-4

2-5 Connecting Cables............................................................................ 2-4

Power Supply Connectors.......................................................... 2-5

Turbo Function.............................................................................. 2-5

USB Connectors........................................................................... 2-7

Reset Cable Connector .............................................................. 2-8

Keylock/Power LED Cable Connector ..................................... 2-8

Keyboard Connector .................................................................... 2-9

Thermal Control Connector ....................................................... 2-9

Hard Drive LED .......................................................................... 2-10

Speaker Cable Connector........................................................ 2-10

PS/2 Keyboard and Mouse Ports ........................................... 2-11

Back-up Cooling Fan and Buzzer Connectors ..................... 2-12

Serial Ports.................................................................................. 2-12

2-6 Installing/Removing the SIMM Modules ...................................... 2-13

SIMM Module Installation.......................................................... 2-13

Removing SIMM Modules ......................................................... 2-14

2-7 Connecting Floppy and Hard Disk Drives.................................. 2-15

Parallel Port Connector ............................................................ 2-16

Floppy Connector ....................................................................... 2-17

IDE Interfaces ............................................................................. 2-18

Chapter 3: Troubleshooting

3-1 Troubleshooting Procedures ........................................................... 3-1

No Video ........................................................................................ 3-1

Troubleshooting Flowchart ........................................................ 3-2

Memory Error................................................................................. 3-3

Losing the System’s Setup Configuration.............................. 3-3

3-2 Technical Support Procedures........................................................ 3-4

3-3 Returning Merchandise for Service................................................ 3-4

SUPER P6DNH/P6DNH2 User's Manual

Table of Contents

vii

SUPER P6DNH/P6DNH2 User's Manual

viii

1-1

Chapter 1: Introduction

Chapter 1

Introduction

1-1 Overview

SUPER P6DNH/P6DNH2 is a high performance, I2OΤΜ enabled com-

puter system board based on Intel®Pentium® Pro 200/180/166/150

MHz processors. They incorporate Intel's 440FX chipset and sup-

port dual processing. SUPER P6DNH uses the 33 MHz i960® RP I/

O processor while SUPER P6DNH2 uses the 66 MHz i960 RD I/O

processor.

The Pentium Pro processor is Intel’s top-of-the-line generation of

performance for servers, workstations, and high-end desktops. It

delivers its superior performance through its Dynamic Execution

microarchitecture which allows multiple branch prediction, dataflow

analysis and speculative execution.

The Pentium Pro processor includes 16KB of internal cache and an

integrated 256KB or 512KB non-blocking secondary cache in the

same package. Having the L2 cache inside the package will not

only save space, it will also have the CPU core communicating with

the L2 cache at full speed. Non-blocking means that the transac-

tions on the processor bus do not block subsequent bus transac-

tions. For example, when a cache miss occurs, the processor will

continue to process other instructions while initiating a bus trans-

action to satisfy the cache miss. These instructions could generate

additional cache misses which could cause more bus transactions.

The Pentium Pro processor can maintain up to four concurrent re-

quests of the bus.

The general purpose registers of the Pentium Pro processor are

the same as on previous generations. The processor bus achieves

high bus efficiency by providing support for multiple, pipelined

transactions and deferred replies. A single processor may have up

to 4 outstanding transactions at the same time. There are a variety

1-2

SUPER P6DNH/P6DNH2 User’s Manual

of wider datapaths both inside and outside the chip. It has an

external 64-bit bus in order to communicate more efficiently with the

system memory. The package have two cavities with about 21 mil-

lion transistors. The larger one is the CPU core with 5.5 million

transistors. The smaller one is the non-blocking cache which con-

tains 15.5 million transistors.

The i960 RP/RD I/O processor is a highly integrated intelligent I/O

subsystem on a chip. Mode 3 is the default setting for its normal

operation. The i960 RP/RD has two main functions. As a local

processor, it offloads interrupt-intensive I/O tasks from the host

CPU. Its architecture is composed of a RISC core surrounded by

peripherals essential to the I/O function. The on-board PCI-to-PCI

bridge enables designers to connect I/O components directly to the

PCI bus and also add additional PCI slots. The bridge improves

overall system performance by reducing bus traffic. SUPER

P6DNH/P6DNH2 supports four primary and four secondary PCI

buses.

I2O is an open software-interface standard for I/O devices, indepen-

dent of the specific device and operating system. It is implemented

on the i960 RP/RD I/O processor. With I2O, I/O hardware vendors

do not have to write drivers in countless variation, one for each

operating system version.

To attain portability across multiple operating systems and host

platforms, I2O drivers are divided into the OS Services Module

(OSM), and Hardware Device Module (HDM). The first module inter-

faces with the host operating system. The second interfaces with

the particular device, media or server managed by the driver. The

two modules interface with each other through a two-layered com-

munications system. A Message Layer sets up a communications

session. A Transport Layer defines how information will be shared.

The Message Layer resides on the Transport Layer.

Peripheral Component Interconnect (PCI) provides industry-leading

performance and compatibility. The 32-bit, 33 MHz pathway to the

CPU offers performance unmatched by other bus architectures. The

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