STMicroelectronics EVALSPEAr320CPU Manual de usuario

EVALSPEAr320CPU

SPEAr320 CPU

evaluation board

UM1015

User manual

Doc ID 18124 Rev 1

October 2010

www.st.com

STMicroelectronics

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October 2010 Doc ID 18124 Rev 1 3/38

UM1015

User manual

EVALSPEAr320CPU

SPEAr320 CPU evaluation board

Introduction

This document applies to revision 2.0 SPEAr320 CPU evaluation boards.

This board can be used to evaluate SPEAr320 microprocessors; the evaluation board kit

comprises one board, one serial cable interface, and one power supply.

CPU board features

■SPEAr320 embedded MPU

■Up to 2 Gbit DDR2 333 MHz (standard 128 Mbytes)

■Up to 16 Mbyte Serial Flash memory (standard 8 Mbytes)

■Two USB 2.0 full host port channels

■One USB 2.0 host device port

■One serial port (up to 115 baud)

■JTAG Debug ports

Figure 1. SPEAr320 CPU evaluation board

Top Bottom

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Contents UM1015

4/38 Doc ID 18124 Rev 1

Contents

1 Getting started . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.1 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.2 Booting procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3 Expansion connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4 Switch and jumper settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.1 Switch 1 settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.2 Switch 2 settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.3 Jumpers and connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5 Board components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6 Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

7 Board layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

8.1 Hardware revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

8.2 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

A License agreements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

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UM1015 List of tables

Doc ID 18124 Rev 1 5/38

List of tables

Table 1. Switch SW1 bits [2:1] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 2. CPU board extension connector J12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 3. CPU board extension connector J13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 4. Switch 1 (SoC functional configuration) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 5. Switch 1 (debug configuration) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 6. Switch 1 (functional configuration) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 7. Switch 2 settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 8. CPU board components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 9. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

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List of figures UM1015

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List of figures

Figure 1. SPEAr320 CPU evaluation board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Figure 2. EVALSPEAr320CPU board block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 3. Serial cable setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 4. 86-pin connectors (J12 and J13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 5. Schematic interconnections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 6. DDR interface schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 7. USB interface schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 8. USB power and optional part schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 9. Miscellaneous interfaces schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 10. Power supply schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 11. Customization interface schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 12. Daughterboard interface schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 13. Schematic revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 14. SPEAr320 CPU evaluation board layout (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 15. SPEAr320 CPU evaluation board layout (bottom view) . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

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UM1015 Getting started

Doc ID 18124 Rev 1 7/38

1 Getting started

Warning: This board contains static sensitive devices.

The EVALSPEAr320CPU board is shipped in protective anti-static packaging. Do not submit

the board to high electrostatic potentials, and follow good practices for working with static

sensitive devices.

●Wear an anti-static wristband. Wearing a simple anti-static wristband can help

prevent ESD from damaging the board.

●Zero potential. Always touch a grounded conducting material before handling the

board, and periodically while handling it.

●Use an anti-static mat. When configuring the board, place it on and anti-static mat to

reduce the possibility of ESD damage.

●Handle only the edges. Handle the board by its edges only, and avoid touching board

components.

1.1 Connections

Refer to Figure 14 on page 31.

1. Connect a serial cable from connector J17 (serial link) to a host PC.

2. On the host PC running Windows or Linux, start the Terminal program.

3. Connect the +5 V voltage adapter (supplied in the EVALSPEAR320CPU package) to

the J11 power voltage connector on the CPU board.

4. Apply power to the board.

5. The Terminal program displays a sequence of boot messages followed by the Linux

console prompt.

For more information, refer to user manual UM0844 Getting started with Linux for SPEAr,

available at www.st.com/spear.

1.2 Booting procedure

The SPEAr320 CPU evaluation board can boot a Linux kernel that has been pre-installed in

the serial NOR Flash.

At power on, the serial port outputs a brief header message with some uBoot information

(uBoot version, SDK version, and some internal hardware information). At this point you can

choose to:

●Stop the system directly in uBoot: Press the spacebar on the host computer

keyboard before the boot delay time expires (default is 3 seconds).

●Boot Linux: The system logs you in automatically as super user, and displays the

Linux shell prompt on the screen.

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Block diagram UM1015

8/38 Doc ID 18124 Rev 1

2 Block diagram

Figure 2. EVALSPEAr320CPU board block diagram

2.0.1 Dynamic memory subsystem

The Dynamic memory subsystem comprises three major parts:

Memory chip

The SPEAr320 MPU supports up to 256 Mbytes of memory. Place and route is provided for

2 chips but only one has been populated. The memory used is a Micron DDR2 device, its

part number is MT47H64M16HR-3 and its size is 128 Mbits x 8 (16 Mbits x 8 x 8 banks).

Local power supply

The local power supply is based on a monolithic voltage regulator for the chip set and

DDR2/3 (PM6641). It is generated locally in order to minimize the layout impact and also to

avoid any noise injection between different subsystems.

Signal termination

A parallel termination is added on the clock lines to compensate, if needed, for the layout

dissymmetry. Two 100k ohm resistors are used for each line in order to obtain an

impedance of 50 ohms. All the other terminations are directly inside the pads (both on the

SPEAr320 MPU and the memory sides).

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UM1015 Block diagram

Doc ID 18124 Rev 1 9/38

2.0.2 Static memory subsystem (Serial Flash memory)

The SPEAr320 MPU supports up to 16 Mbytes of Serial Flash memory. Place and route for

2 blocks of 8 Mbytes are provided on the board, but only one is populated. It is based on an

M25P64-VMF6P (Numonix) Serial Flash memory device.

Resistor R8 protects the Flash memory from any unwanted write access.

2.0.3 USB 2.0 subsystem

Host ports

The board has two host ports that are fully compliant with the USB 2.0 specification (two

controllers with one port each). This means that the two hosts can work in concurrent mode

with the maximum possible bandwidth. Each host has also full control of the VBUS supplied

by the ST2052 power switch that also provides over current protection in case of a short

circuit in the USB cable.

Device port

The board has one USB 2.0 device port.

2.0.4 Debug interface

The JTAG interface can be used for static debugging, which means that it is possible to set

a breakpoint, and when the system stops, verify the contents of the memory or registers, or

both, and modify them if needed.

To select the debug feature, set Switch SW1 bits [2:1].

For more information on the ETM interface, refer to the trace box manufacturer’s

documentation (www.lauterbach.com, www.agilent.com, www.yokogawa.com).

2.0.5 Serial interface

One serial interface port is available. Typically used as an OS monitor, this port is available

on the J17 connector. It is possible to simulate a cross cable by changing the position of the

J22 jumpers.

Figure 3. Serial cable setting

Table 1. Switch SW1 bits [2:1]

Bit 2 Bit 1 Description

0 0 No debug features available

0 1 The ARM JTAG is connected to J4

Nul

Modem

Cable

J22

Cross

Cable

J22

Block diagram UM1015

10/38 Doc ID 18124 Rev 1

2.0.6 Real time clock (battery powered)

The real time clock (RTC) is powered by an external battery (3V) in order to prevent data

loss even if the main power supply is switched off.

2.0.7 General power supply

From a 5 V external AC/DC regulator power source, this block generates all the required

voltages as follows:

●1.2V (Switching regulator PM6641) to supply the internal logic of the SPEAr320 MPU

●1.8V (Switching regulator PM6641) for the DDR2 memory

●2.5V (LDO regulator) for the analog portion of SPEAr320

●3.3V (Switching regulator PM6641) to supply the other interfaces

A power monitor is also present to provide the general reset of the board.

2.0.8 Reset button

A manual reset button (P1) on the top of the board (see Figure 14 on page 31) resets the

microprocessor on the core board.

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