Sinclair Research ZX Spectrum Manual de usuario

SERVICINGMANUAL

FOR

ZXSPECTRUM®

•LISTOFCONTENTS

INTRODUCTION

SECTION1 SYSTEMDESCRIPTION

SECTION2 DISASSEMBLY/ASSEMBLY

SECTION3 SETTINGUPANDSYSTEMTEST

SECTION4 FAULTDIAGNOSISANDREPAIR

SECTION5 PARTSLISTS

iLISTOFILLUSTRATIONSi

FigNo.

ZXSpectrumBlockDiagram1.1

ExpansionRAMRAS/CASTiming(ReadCycleshown)1.2

KeyboardMatrixInterconnections1.3

ZXSpectrum(Issue2)CircuitDiagram1.4

ZXSpectrum(Issue3)CircuitDiagram1.5

KeyboardFormat4.1

SpeakerLoadInputWaveforms4.2

ExpansionMemory1CLocations4.3

Issue3 Linksvs1CManufacturerandType4.4

PrintedCircuitBoard(Issue2)ComponentLayout5.1

PrintedCircuitBoard(Issue3)ComponentLayout5.2

PrintedCircuitBoard(Issue3B)ComponentLayout5.3

Prepared

THORN

(EMI)

DATATECH

LTD

forSINCLAIRRESEARCHLTDMARCH1984

©SinclairResearchLtd.

(i)

-INTRODUCTION

This

manual

isforuseby

authorised

SINCLAIR

dealers,engineersandrepresentativesasa guide

rectifying

faults

onthe

SINCLAIR

SPECTRUM

personalcomputer.

ThemanualrefersprincipallytotheIssue2 and

Issue3 Spectrumsbutprovidesa backgroundtothe

Issue1 versioninthesectiondealingwith

modificationhistory.

Basic

knowledge

ofZX

SPECTRUM

operating

proceduresisassumedasisknowledgeofcurrent

workshoppracticerelatingtomicrocomputers.

NOTE:

Essentialmodifications

are

required

onsomeIssue2 Spectrums.Referto

ModificationHistory(Section4)and

implementasnecessary.

-SAFETYMEASURES•

Thisinstructionmanualcontainscertain

—WARNING— andCAUTION-

noticeswhichMUSTbe-followedbytheuserto

ensureSAFEoperationandtoretainthe

equipmentina SAFEcondition.

Anyadjustment,maintenanceandrepairofthe

openedapparatusundervoltageshallbe

carriedcutonlybya skilledpersonwhois

AWAREOFTHEHAZARDINVOLVED.

SECTION1

SYSTEMDESCRIPTION

Sub-SectionLISTOFCONTENTSPageNo.

1Introduction1.1

2Architecture1.1

3Z80ACPU1.2

4MemoryOrganisation1.4

Read/WriteOperations1.4

5Input/Output1.6

TVPictureGeneration1.6

KeyboardScanning1.8

TapeInterface1.10

6PowerSupplies1.11

CircuitDiagrams

ZXSpectrum,Issue2 Fig.1.4

ZXSpectrum,Issue3 Fig.1.5

1.INTRODUCTION

1.1A blockdiagramofthecompleteZXSPECTRUMmicro-computerisgivenin

Figure1.1.Itisvalidforallbuildstandards,fittedwitheither

16kor48kbytesofdynamicRAMmemory.Althoughfunctionally

identical,detailedcircuitchangeshavebeenintroducedtoimprove

reliabilityandtoassistwithmanufacture.Theprintedcircuitboard

layouthasalsobeenmodified.Detailsofthesechangesare

highlightedwherenecessaryinthefollowingparagraphs,andinlater

sectionsreferringtofaultdiagnosisandrepair.

2.ARCHITECTURE

2.1The

architecture

ofthe

Spectrum

shown

Figure

1.1is

typical

many

microcomputersystems

that

comprises

single

microprocessorboard

(in

this

instance

Z80A

oru 780

CPU),

read

only

memory

(ROM),

expandable

RAM

memory

andan

input/output

sectionhandlingthekeyboard,tapeandTVdisplayfunctions.The

latterisrecognisableasthelogicgatearray(ULA)andthethree

functionalblocks

shown

inthe

right

ofthe

diagram.

2.2The

computer

built

ona

single

printed

circuit

boardwhich

also

includesa regulatedpowersupplyfedfromanexternal9Vpowerpack.

Thekeyboardmatrixispartoftheuppercaseassemblyandis

connectedtotheboardviatworibboncablesKB1andKB2.A

descriptionofeachsectionfollows.

1.1

3.Z80ACPU

3.1The

Z80A

isan

8-bit

single-IC

central

processing

unit

(CPU).

Itis

clocked

14.0

MHz

from

externalsourcecontrolled

bythe

logic

gatearray(ULA)andhasa standardthreebusinput/output

arrangement.ThesebusesaretheDataBus,AddressBusandControl

Busrespectively.

3.2

Data

Bus.

D7-D10

constitutes

8-bit

bi-directional

data

bus

with

active

high,

tri-state

input/outputs.

Itis

used

for

data

exchanges

withthememoryandwiththeULA.

3.3

Address

Bus.

A15-AO

constitutes

16-bit

address

bus

with

active

high,tri-stateoutputs.Theaddressbusprovidestheaddressfor

memory(upto64kbytes)dataexchangesandfordataexchangeswith

theULA.Itisalsousedduringtheinterruptroutine(seebelow)

whenscanningthekeyboardmatrix.

3.4ControlBus.Thecontrolbusisa collectionofindividualsignals

whichgenerallyorganisetheflowofdataontheaddressanddata

buses.Theblockdiagramonlyshowsfiveofthesesignalsalthough

othersofminorimportancearemadeavailableattheexpansionport

(seeFigures1.4and1.5fordetails).

3.5

Starting

with

memory

reguest

fMREQ),

this

signal

active

low

indicating

when

the

address

bus

holds

valid

address

fora

memory

read

memory

writeoperation.Input/Outputreguest

(IORQ)

also

active

lowbut

indicates

when

the

lowerhalf

ofthe

address

bus

holds

avalidI/OaddressfortheULAduringI/Oread/writeoperations.

3.6Thereadandwritesignals(RDandWR)areactivelow,andoneor

otherisactiveindicatingthattheCPUwantstoreadorwritedatato

memory

location

orI/O

device.

Allthe

control

signals

discussed

farareactivelow,tri-stateoutputs.

Thecontrolsignaldescribedhereistheinterrupt

3.7

last

maskable

(INT).

This

input

active

lowandis

generated

bytheULA

once

every20ms.EachtimeitisreceivedtheCPU'calls'the'maskable

interrupt'routineduringwhichthereal-timeisincrementedandthe

keyboardisscanned.

3.8CPU

Clock.Returning

totheCPU

clock

mentioned

earlier

this

section,theULAisabletoinhibitthisinputbringingtheCPUtoa

temporary

halt.

This

mechanism

gives

theULA

absolute

priority,

allowingittoaccessthestandard16kRAMwithoutinterferencefrom

theCPU(seeRAMdescription).SwitchingtransistorTR3ensuresthat

theclockamplitudeis+5VratherthansomearbitraryTTLlevel.This

isessentialiftheCPUistooperateeffectivelywhileexecutingfast

machinecodeprogramsofthe'spaceinvader'^'

1.2

3.9

Dynamic

Memory

Refresh.

TheCPU

incorporates

built-in

dynamic

RAM

refreshcircuitry.AspartoftheinstructionOPcodefetchcycle,

theCPU

performs

memory

requestafter

first

placing

the

refresh

addressonthelowereightbitsoftheaddressbus.Attheendofthe

cycletheaddressisincrementedsothatover255fetchcycles,each

rowofthedynamicRAMisrefreshed.Thismechanismonlyappliesto

theoptional32kexpansionRAMinthe48kSpectrum.Analternative

refreshmethodisadaptedforthestandard16KRAM.

4.MEMORYORGANISATION

4.1Inthe

standard

16k

Spectrum

there

are32k

bytes

addressable

memory

equallydividedbetweenROMandRAM.

4.2The

lower

16k

bytes

memory

(addresses

0000

3FFF)

are

implemented

ina singleROM(IC5)whichholdsthemonitorprogram.Thisprogram

isa complexZ80machinecodeprogramdividedbroadlyintothreeparts

one

eachcovering

the

input/outputroutines,

the

BASIC

interpreter

and

expressionhandling.Detailsoftheprogramcontent,althoughoutside

the

scope

this

manual,

are

referred

toas

necessary.

4.3The

upper

bytes

memory

(addresses

4000

7FFF)

are

implemented

using

eight

16kbit

dynamic

RAMs

(IC6-IC13).

Approximatelyhalf

this

space

available

tothe

user

for

writing

BASIC

machine

code

programs.Theremainderisusedtoholdthesystemvariables

including6kbytesreservedforthememorymappeddisplayarea.

4.4Inthe48kSpectrumanadditional32kbytesofRAMareprovided

(addresses

8000

FFFF)

which

are

implementedusing

eight

32kbit

dynamic

RAMs

(IC15-IC32).

The

RAM,providing

extra

memory

space

for

theuser,isnormallyfittedduringmanufacturebutmaybeadded

retrospectively

using

the

RAM

expander

kit.

addition

tothe

RAMs,

thekitincludestheaddressmultiplexerandread/writecontrolICs

IC23-IC26.

Board

space

andthe

necessary

discrete

components

are

alreadyprovidedontheboard.

4.5Read/WriteOperations

4.5.1Thefollowingdescriptionshouldbereadinconjunctionwiththe

circuitdiagramsgiveninFigures1.4and1.5.

4.5.2ReadOnlyMemory(ICS).TheCPUaddressestheROMdirectlyduring

memoryreadcyclesusingtheaddressbusA13-AO.MREQandRDenable

theROMandtheROMoutputsrespectively.A thirdinput(CS)derived

bytheULA'ROMCS)selectstheROM,providedthehigherorderaddress

bitsA14andA15arebothlow.Thesearereservedforaccessingthe

RAMmemorywhichstartswithaddress4000(i.e.addressA14set).An

externalROM1Cselectinput,suppliedviatheexpansionportonpin

25A,selectivelydisablestheon-boardROMbypullingtheselectinput

high.ByvirtueofR33placedontheULAsideoftheROMtheULA

ROMCSoutputiseffectivelyinhibited.Interface1 usesthis

1.4

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