AN45
8 Rev. 0.61
1.5.1. Undervoltage Lock-Out
The undervoltage lock-out is implemented via the
SDCH pin as shown in Figure 5. When the VDC goes
under a specified value, the current flow through R19
into the SDCH pin goes under 120 A, and it triggers
the Si321x to shut off the dc-dc converter. The equation
for R19 with a specific VDC is given by the following:
Equation 20
R19 should be calculated with a 20% lower value in VDC
to prevent premature low-voltage lock-out. If the voltage
lock-out is activated too often or if the Si321x goes in
and out of low-voltage lock-out and creates an
oscillation-like condition at the input voltage, it indicates
that the input power source has high impedance and
should be replaced with a better power source.
However, the values of R18, R19, and R20 should be
checked against the intended low-voltage lock-out
before any conclusion is made about the input power
source.
1.5.2. Overcurrent Protection
Overcurrent protection is implemented via the SDCL
pin. (See Figure 5.) The circuit is designed to produce
equal current flow from VDC to both the SDCL and
SDCH pins with zero current flow through Q7. (R20 is
set to be equal to R19 and the value of R18 is small.)
When current flows through Q7, it generates a voltage
drop across R18 and reduces the current flow into the
SDCL pin. When the current flow into the SDCL pin is
10.5 A lower compared to the current flow into the
SDCH pin, it triggers the overcurrent protection, and the
Si321x ends the current PWM cycle to prevent
excessive current flow through Q7. The overload
current should be set 20% above the maximum inductor
current to prevent current shut down prematurely.
Equation 21
A fuse or other power overload circuit should be placed
between the VDC power supply and each input of the
ProSLIC dc-dc converter circuit (one per ProSLIC
solution) to protect the switching components (Q7 or
M1) from potential electrical overstress in the event of a
hardware fault condition. For more information
concerning fuse selection, please contact Silicon Labs.
1.6. Output Overvoltage Protection
It is possible for the dc-dc converter to generate
excessively high voltage beyond the voltage rating of
external components. To prevent damage to these
components, a transistor (Q9) is added to limit the VBAT
to a desired level.
Resistors R28 and R29 are connected between VCC
and VBAT as a biasing circuit for the transistor, Q9.
When VBAT approaches the predetermined voltage
level set by R28 and R29, Q9 is turned on and takes
current from R20 away from pin SDCL and,
consequentially, triggers the Si321x to end its current
PWM cycle.
Q9 can be any NPN low voltage (12 V or higher)
general-purpose transistor (2N2222 is recommended).
The equations for R28 and R29 are as follows:
where VBE = .55 V.
where VCLAMP is the clamping voltage for VBAT.
VCLAMP should be set to a voltage less than the voltage
rating of the external components and higher than the
maximum VBAT to be generated for a given application.
1.7. Design Example
Suppose that the system requires 5REN of loading on
1680 ft. of line length with a ringing signal 45 V RMS at
the phone. The fast voltage measurement feature is not
supported, and the system prefers optimization for
power saving. The system has regulated 5 V as the
main supply voltage for the Si321x and an unregulated
12 V dc with a .75 A current rating.
1.7.1. Step 1: Define the Output Requirement
Calculate VTR_PK from Equation 1:
From Equation 2:
R19
VDC
1.5
-------------0.8–
120 A
--------------------------- 4.5 k–=
R18 10.5 A4.5 kR19,20
+
1.2 IOVERLOAD
---------------------------------------------
=
R28 VCC VBE+
148 A
-------------------------------------
=
R29 VCLAMP
148 A
---------------------
=
VTR_PK
VRINGrms 2
7000 NREN
--------------------------------------- 7000
NREN
------------------2 Dist 0.045 160++
=
VTR_PK
45 2
7000 5
-------------------- 7000
5
-------------2 1680 045 160++
76.5==
VBAT VTR_PK VCMR+76.5 1.5+78 V===
