9 Core-Local Interruptor (CLINT).....................................................................44
9.1 CLINT Memory Map.................................................................................................. 44
9.2 MSIP Registers......................................................................................................... 45
9.3 Timer Registers ........................................................................................................ 45
10 Platform-Level Interrupt Controller (PLIC)...........................................46
10.1 Memory Map .......................................................................................................... 46
10.2 Interrupt Sources .................................................................................................... 47
10.3 Interrupt Priorities.................................................................................................... 48
10.4 Interrupt Pending Bits ..............................................................................................48
10.5 Interrupt nables..................................................................................................... 49
10.6 Priority Thresholds .................................................................................................. 50
10.7 Interrupt Claim Process ...........................................................................................51
10.8 Interrupt Completion................................................................................................51
10.9 rror Device ........................................................................................................... 52
11 One-Time Programmable emory (OTP) Peripheral......................53
11.1 Memory Map .......................................................................................................... 53
11.2 Programmed-I/O lock register (otp_lock)................................................................54
11.3 Programmed-I/O Sequencing...................................................................................55
11.4 Read sequencer control register (otp_rsctrl)........................................................55
11.5 OTP Programming Warnings....................................................................................56
11.6 OTP Programming Procedure ..................................................................................56
12 Always-On (AON) Domain ............................................................................57
12.1 AON Power Source.................................................................................................58
12.2 AON Clocking......................................................................................................... 58
12.3 AON Reset Unit ...................................................................................................... 58
12.4 Power-On Reset Circuit ...........................................................................................58
12.5 xternal Reset Circuit..............................................................................................59
12.6 Reset Cause........................................................................................................... 59
12.7 Watchdog Timer (WDT) ...........................................................................................59
12.8 Real-Time Clock (RTC)............................................................................................59
F 310-G003 Manual © SiFive, Inc. Page 3
