Samsung SGH-D730 Manual de usuario

MITs TELEPHONE

SGH-D730

MITs TELEPHONE CONTENTS

1. Specification

2. Flow Chart of Troubleshooting

3. Exploded Views and Parts List

4. Electrical Parts List

5. PCB Diagrams

6. Block Diagrams

1. SGH-D730 Specification

1-2

1-1. GSM General Specification

GSM900

Phase 1

EGSM 900

Phase 2

DCS1800

Phase 1 PCS1900

Freq. Band[MHz]

Uplink/Downlink

890~915

935~960

880~915

925~960

1710~1785

1805~1880

1850~1910

1930~1990

ARFCN range 1~124 0~124 &

975~1023 512~885 512~810

Tx/Rx spacing 45MHz 45MHz 95MHz 80MHz

Mod. Bit rate/

Bit Period

270.833kbps

3.692us

270.833kbps

3.692us

270.833kbps

3.692us

270.833kbps

3.692us

Time Slot

Period/Frame

Period

576.9us

4.615ms

576.9us

4.615ms

576.9us

4.615ms

576.9us

4.615ms

Modulation 0.3GMSK 0.3GMSK 0.3GMSK 0.3GMSK

MS Power 33dBm~13dBm 33dBm~5dBm 30dBm~0dBm 30dBm~0dBm

Power Class 5pcl ~ 15pcl 5pcl ~ 19pcl 0pcl ~ 15pcl 0pcl ~ 15pcl

Sensitivity -102dBm -102dBm -100dBm -100dBm

TDMA Mux 8 8 8 8

Cell Radius 35Km 35Km 2Km -

SGH-D730 Speclflcation

1-2

1-2. GSM Tx Power Class

TX Power

control level GSM900

5 33±2 dBm

6 31±2 dBm

7 29±2 dBm

8 27±2 dBm

9 25±2 dBm

10 23±2 dBm

11 21±2 dBm

12 19±2 dBm

13 17±2 dBm

14 15±2 dBm

15 13±2 dBm

16 11±3 dBm

17 9±3dBm

18 7±3 dBm

19 5±3 dBm

TX Power

control level DCS1800

0 30±3 dBm

1 28±3 dBm

2 26±3 dBm

3 24±3 dBm

4 22±3 dBm

5 20±3 dBm

6 18±3 dBm

7 16±3 dBm

8 14±3 dBm

9 12±4 dBm

10 10±4 dBm

11 8±4dBm

12 6±4 dBm

13 4±4 dBm

14 2±5 dBm

15 0±5 dBm

TX Power

control level PCS1900

0 30±3 dBm

1 28±3 dBm

2 26±3 dBm

3 24±3 dBm

4 22±3 dBm

5 20±3 dBm

6 18±3 dBm

7 16±3 dBm

8 14±3 dBm

9 12±4 dBm

10 10±4 dBm

11 8±4dBm

12 6±4 dBm

13 4±4 dBm

14 2±5 dBm

15 0±5 dBm

SAMSUNG Proprietary-Contents may change without notice

2. SGH-D730 Flow Chart of Troubleshooting and Circuit Diagrams

2-1

This Document can not be used without Samsung's authorization

2-1.Baseband

2-1-1. Power ON

Check the current

consumtion more than

100mA

Check the Vbat(battery+O)

Voltagemorethan3.3V

Downloader again

Charge the Battery

Check CN304,C387

YES

'Power On' does not work

Check the pin

4 of Q303 is more

than 3.3V

Check the pin

1 of Q303 is more

than 3.3V

U100 pin A19

=3.0V

YES

Check Q303,Q305 and D302

Check U308,U100 and C109

U100 pin B14

=1.8V

YES

Check U308,U100 and C106

U100 pin A15

=1.6V

YES

Check U304,U100 and C101

'Power On' does not work

END

Check the clock signal

at pin1 of OSC100

Freq=12MHz

Check the clock generation circuit

(OSC100)

YES

①

②

③

④

⑤

⑥

SAMSUNG Proprietary-Contents may change without notice

SGH-D730 Flow Chart of Troubleshooting and Circuit Diagrams

2-2

This Document can not be used without Samsung's authorization

SAMSUNG Proprietary-Contents may change without notice

SGH-D730 Flow Chart of Troubleshooting and Circuit Diagrams

2-3

This Document can not be used without Samsung's authorization

Q101

R129

C143

R111

VDD_30D

R109

TP103

R121

VDD_30DVDD_30D

R144

R123

R113

VDD_30D

VDD_18D

C102

C120

Q102

C141

VDD_18D

R122

R130

R165

VDD_30D

C103

C115

R120

VDD_15D

C140

VDD_30D

C142

TP101

C101

VDD_30D

C145

OSC100

GND1

GND2

HOT

R100

VDD_30D

VDD_15D

C144

R164

R108

TP104

R114

R166

R147

R168

R110

C100

R148

R139

R112

VDD_18D

VDD_30D

33PFC715

R107

R126

C104

W13

WA-KEUP_INT

WIRE_SCLK

V19

WIRE_SDI

U18

W21 WIRE_SDO

N14 Z_STATE1

Z_STATE2

P15

Z_STATE3

W16

VDD_2

Y20

Y9 VDD_3

VDD_4

W12 VDD_RTC

L1 VPP

VDDSHV4_3 A7

VDDSHV4_4 R1

VDDSHV5_1

VDDSHV5_2 H2

VDDSHV5_3

VDDSHV6 AA11

Y16

VDDSHV7

VDDSHV8 L21

U21

VDDSHV9

VDDSHV_RTC V12

A15 VDD_1

VDD3_2

B20

J21 VDD3_3

VDD3_4

R20

VDDA

Y21 VDDSHV1_1 A19

E21

VDDSHV1_2

VDDSHV2 AA2

VDDSHV3

VDDSHV4_1 B14

B10

VDDSHV4_2

TMS

V17

Y15 UARTS_CLKIO

UARTS_CLKREQ

W15

USB_DM

USB_DP P9

USB_PUEN

AA3 VDD1

VDD2_1

A9 VDD2_2

VDD2_3

B13 VDD3_1

SDATA_5

SDATA_6

SDATA_7

C10 SDATA_8

SDATA_9

D14

SDCLK

C9 SDCLKX

SDCLK_EN

H12

W18 TCK

TDI

Y19

AA19 TDO

SDATA_1

SDATA_10

D11

SDATA_11

C13

SDATA_12

C11

SDATA_13

D13

SDATA_14

D12

SDATA_15

C12

C5 SDATA_2

SDATA_3

SDATA_4

SADD_4

G10

SADD_5

SADD_6

G12

SADD_7

G11

SADD_8

SADD_9

B12

SBANK_0

C3 SBANK_1

SCL

T18

V20 SDA

SDATA_0

RX1

V14

R9 RX2

RX3

L14

SADD_0

SADD_1

B8 SADD_10

SADD_11

H10

SADD_12

H11 SADD_13

SADD_2

SADD_3

NSWE

NTRST

Y18

ON_NOFF Y12

OSC1_IN Y2

OSC1_OUT

P12

RE-SET_MODE

Y17 RTCK

NFCS_3 N8

NFOE U4

NFRP

NFWE W2

NFWP

NRE-SET_OUT

AA20

NRESPWRON R12

NSCAS

NSDQML

NSDQMU

D10

NSRAS

NC1 1

NC2

V16 NEMU0

NEMU1

W17

NFADV L4

NFBE_0

NFBE_1 M8

NFCS_1 M3

NFCS_1B Y1

NFCS_2

NFCS_2B

Y10

AA9

MCSI2_DIN

MCSI2_DOUT W9

MCSI2_SYNC

V11

MMC_CLK P11

MMC_CMD

MMC_DAT0 R11

MMC_DAT1 V10

W10

MMC_DAT2

MMC_DAT3 W11

MPU_NRE-SET

U20

MCBSP2_CLKR V7

MCBSP2_CLKX

MCBSP2_DIN P10

MCBSP2_DOUT AA5

MCBSP2_RSYNC

MCBSP2_XSYNC

P14 MCSI1_BCLK

V15 MCSI1_DIN

MCSI1_DOUT

W14

MCSI1_SYNC

AA17

MCSI2_CLK

LCD_PIX-EL_6

B19

C18 LCD_PIX-EL_7

LCD_PIX-EL_8

D17 LCD_PIX-EL_9

D16

B18 LCD_VSYNC

MCBSP1_BCLK

G21

G20 MCBSP1_CLKS

H20 MCBSP1_DIN

MCBSP1_DOUT

H18

H15 MCBSP1_SYNC

LCD_PIX-EL_10

C17 LCD_PIX-EL_11

B17 LCD_PIX-EL_12

G13 LCD_PIX-EL_13

A17 LCD_PIX-EL_14

C16 LCD_PIX-EL_15

D15

LCD_PIX-EL_2

C19

G14 LCD_PIX-EL_3

LCD_PIX-EL_4

H13

A20 LCD_PIX-EL_5

KBC_5

G19

G18 KBR_0

KBR_1

F19

H14 KBR_2

KBR_3

E20

E19 KBR_4

B15 LCD_AC

C20 LCD_HSYNC

LCD_PCLK

C15

LCD_PIX-EL_0

D18

B21 LCD_PIX-EL_1

GPIO_4 P20

GPIO_6 P19

GPIO_62

GPIO_7 M15

GPIO_8 Y8

GPIO_9

KBC_0

F18

D20 KBC_1

KBC_2

D19

E18 KBC_3

KBC_4

C21

FRDY V2

GPIO_0 R18

GPIO_1 R19

GPIO_11 N20

GPIO_12 N18

GPIO_13 N19

GPIO_14 N21

M20

GPIO_15

GPIO_2 M14

P18

GPIO_3

FDATA_13 U3

FDATA_14

FDATA_15

FDATA_2 N7

FDATA_3 P2

FDATA_4

FDATA_5 P7

FDATA_6

FDATA_7 R3

FDATA_8

FDATA_9

FADD_5

FADD_6 F4

FADD_7

FADD_8 J7

FADD_9 F3

FCLK

FDATA_0 N4

FDATA_1

FDATA_10

FDATA_11 P8

FDATA_12

FADD_19

FADD_2 D3

FADD_20

FADD_21 L8

FADD_22

FADD_23 K3

FADD_24

FADD_25

FADD_3

FADD_4 E4

DQS_L

FADD_1

FADD_10 G4

FADD_11

FADD_12 G2

FADD_13

FADD_14 H4

FADD_15

FADD_16 K7

FADD_17

FADD_18

CAM_VS L18

CDD_DLL

A11

P13 CLK32K_IN

R13 CLK32K_OUT

COM_MCLK_OUT V5

COM_MCLK_REQ R10

V18 CONF

CS_SDRAM

R14 CTS1

CTS2 Y5

DQS_H

C14

K14

CAM_D_2 K15

CAM_D_3 K19

K18

CAM_D_4

CAM_D_5 J14

CAM_D_6 J19

CAM_D_7 J18

CAM_EXCLK H19

CAM_HS L15

CAM_LCLK J15

CAM_RSTZ M19

M18

0_STATE5

U19 ARMIO_1

N15 ARMIO_2

V8 ARMIO_3

ARMIO_4

T19

T20 ARMIO_5

ARM_BOOT

J20

BDCLK2

W19 BVLZ

CAM_D_0 L19

CAM_D_1

U100

0_STATE1 AA15

Y14

0_STATE2 W5

0_STATE3

0_STATE4 V6

OPEN_SENSE

CAM_MCLK

CD_CLK_12M

UDQM

LDQM

SCLK

BP_VF

DEBUG_RXD

PH_PWR_ON

PDA_ACTIVE

PDA_WAKEUP

PH_WAKEUP

CLK32K_OMAP

BT_CTS

CAM_EN

BT_REQ

JIG_ON

KB_LED_EN

FA(14)

FA(16)

FA(17)

FA(18)

FA(19)

FA(20)

FA(21)

FA(22)

FA(23)

FA(24)

FA(25)

FA(13)

AP_AT_nDSR

LCD_BL_EN

FD(13)

FD(14)

FD(15)

FA(1:25)

FA(1)

FA(2)

FA(3)

FA(4)

FA(5)

FA(7)

FA(9)

FA(10)

FA(12)

SA(3)

SA(4)

SA(5)

SA(6)

SA(7)

SA(8)

SA(9)

SA(10)

SA(11)

SA(12)

SA(0)

FD(8)

FD(9)

FD(10)

FD(11)

FD(12)

SD(0)

CAM_SCL

FA(6)

FA(8)

FA(11)

FA(15)

nBAT_LOW

NFWE

NFOE

FD(0:15)

OMAP_RTCK

OMAP_TRST

SA(0:12)

SA(1)

SA(2)

IIS_LRCK

IIS_SDO

IIS_SDI

AP_AT_nDTR

CODEC_CSB

LCD_SCL

OMAP_EMU0

OMAP_EMU1

nSRAS

USB_DP

USB_D

LCD_VDD_EN

LCD_B2

LCD_B1

LCD_B0

LCD_HSYNC

KB_nSCAN(5)

KB_nSCAN(4)

KB_nSCAN(3)

KB_nSCAN(2)

KB_nSCAN(1)

KB_nSCAN(0)

KB_nIN(4)

KB_nIN(3)

KB_nIN(2)

KB_nIN(1)

KB_nIN(0)

IIS_SCLK

LCD_ENABLE

LCD_DOTCLK

LCD_VSYNC

LCD_R4

LCD_R3

LCD_R2

LCD_R1

LCD_R0

LCD_G5

LCD_G4

LCD_G3

LCD_G2

LCD_G1

LCD_G0

LCD_B4

LCD_B3

SD(2)

SD(3)

SD(4)

SD(5)

SD(6)

SD(7)

SD(8)

SD(9)

SD(10)

SD(11)

SD(12)

SD(13)

SD(14)

SD(15)

BT_RXD

AP_AT_RXD

OMAP_TCK

OMAP_TDI

OMAP_TDO

OMAP_TMS

PUEN

VDD_SHV2

CODEC_SCK

CODEC_SDO

CODEC_SDI

LCD_CS

VIB_EN

SD(0:15)

SD(1)

MMC_SCLK

MMC_CMD

MMC_DAT

SW_RST_INT

FLASH_EN

NFCS_3

OHP_nRESET

nSCAS

nSWE

SBANK_0

SBANK_1

CAM_SDA

SCKE

FD(4)

FD(5)

FD(6)

FD(7)

LCD_SDI

PH_OFF_nRDY

JACK_nSEND_END

FLIP_SENSE

ON_SW_SENSE

MMC_nInserted

USB_nINSERTED

JACK_SENSE

LCD_RESET

BT_nSHDN

PWR_HOLD

CAM_HSYNC

CAM_PCLK

CAM_RESET

CAM_VSYNC

nCS_SDRAM0

AP_AT_nCTS

FD(0)

FD(1)

FD(2)

FD(3)

PH_ACTIVE

BT_RTS

BT_TXD

AP_AT_nRTS

AP_AT_TXD

DEBUG_TXD

SAMSUNG Proprietary-Contents may change without notice

SGH-D730 Flow Chart of Troubleshooting and Circuit Diagrams

2-4

This Document can not be used without Samsung's authorization

C316

D302

U305

EMD6

V_IN

R332

VDD_30D

D301

R324

VRTC G

Q303 1256

C308

C315

VBAT

C309

R336

Q306

Q305

RTC_nALARM ON_SW_SENSE

JIG_ON

PWR_ON_AP

PWR_HOLD

R613

VDD_15D

L600

GND

MODE/SYNC

PGND

VIN

VOUT

V_IN

U604

AGND

AVIN

SAMSUNG Proprietary-Contents may change without notice

SGH-D730 Flow Chart of Troubleshooting and Circuit Diagrams

2-5

This Document can not be used without Samsung's authorization

2-1-2. Initial

U400 pin C16

=1.8V

Check the

pin F4 of

U400 is "High"

Check U301

Check the U400

YES

Initial Failure

U400 pin B14

=3.0V Check the U400

YES

Check and resolder LCD connector CN303

if there is solder bridge between the pins

END

YES

Check the U400

YES

Check the clock

signals at

pin3 and pin5 of

OSC400

Freq=13MHz

Check the clock generation circuit

(OSC400)

Check the pin C12

of U500 is "High" Check U500

YES

Check the

pin 2 of

U301 is "High"

①

②

③

④

⑤

⑥

SAMSUNG Proprietary-Contents may change without notice

SGH-D730 Flow Chart of Troubleshooting and Circuit Diagrams

2-6

This Document can not be used without Samsung's authorization

①

②③④

⑤

⑥

SAMSUNG Proprietary-Contents may change without notice

SGH-D730 Flow Chart of Troubleshooting and Circuit Diagrams

2-7

This Document can not be used without Samsung's authorization

OSC401

VRTC

R413

DSP_TDI

TP405

TP403

R416

VCCD

TP407

VDD_18D

R414

VCCB

R410

C407

R441

R440

VDD_30D

C422

DSP_TMS

D12

C411

XPA6/BE1N

XPA7/IRQ1

T5 XPA8/IRQ2

XPA9/IRQ3

XRTCALARM_N

XTIC_MODE

XPA3/CS4N

N14

XPA4/OEN

P16

XPA5/WAITN

P15

T15

M11 XPA2/CS3N

M14 XPA1/CS2N

C13 XCP_WEN

XOSC32OUT

XPA0/CS1N

M15

N2 XPA10/IRQ4

XCP_D6

D5 XCP_D7

C4 XCP_D8

XCP_D9

XCP_D11

XCP_D12

D2 XCP_D13

D3 XCP_D14

XCP_D15

F8 XCP_D2

XCP_D3

C5 XCP_D4

XCP_D5

XCP_A8

B17

C17 XCP_A9

A13 XCP_CSRAMEN

XCP_CSROMEN

A12

XCP_D0

B5 XCP_D1

XCP_D10

XCP_A2

E14

XCP_A20

L15

L16 XCP_A21

D15 XCP_A3

B15 XCP_A4

XCP_A5

C14

A16 XCP_A6

XCP_A7

A15

XCP_A12

G14

G13 XCP_A13

XCP_A14

G17

J12 XCP_A15

K12 XCP_A16

XCP_A17

K13

K14 XCP_A18

XCP_A19

L14

A11

XAG2 E11

D11

XAG3

XBSWN

XCPTSTSTOP_CKO M12

B13 XCP_A0_BEON

F11 XCP_A1

D16 XCP_A10

XCP_A11

F14

X1RTC

D10

X2RTC

B11

XAG0

XAG1

H12

F12

TDO

G12

TMS

TRST F15

IO7

IOBIT#1 K11

IOBIT#2 L12

RWN U5

TCK H13

TDI

DB#4

DB#5

DB#6 R7

DB#7

DB#8

DB#9 N7

INT#0 R12

DB#1

DB#10 N8

DB#11

DB#12 U11

T11

DB#13

R11

DB#14

DB#15 P10

DB#2

DB#3 P6

P12

AB#5

AB#6 R14

AB#7 T14

T17

AB#8

G15

CKO

DB#0 P5

U400

U13

AB#0

AB#1 M10

R13

AB#2

N11

AB#3

AB#4 P11

R404

DSP_TDO

VCCD

C424C423

VS 1

R407

U402

GND

2VO

C406

R402

DSP_TCK

TP404

R408

VDD_18D

R415

VDD_18D

VBAT

R403

R409

TP406

VCCD

C410

SVC_BLUE

PH_PWR_OFF

CLK32K

JACK_SENSE

BP_VF

DSP_AB(8)

ARM_TRSTN

UP_SCLK

UP_CS

FLASH_RESET

VREF

CP_CSROM2EN

SW_RST_INT

A(23)

BT_REQ

SIMRST

RTC_nALARM

TR_RST

ARM_TCK

DSP_DB(0:15)

D(0:15)

A(0:20)

A(21)

AT_nRTS

DSP_AB(0:8)

UP_SDI

UP_SDO

ARM_TDO

ARM_TRSTN

ARM_TDI

ARM_TMS

PH_WAKEUP

AT_nDTR

PH_OFF_nRDY

AT_nDSR

PWR_KEEP

AT_TXD

AT_nCTS

PDA_WAKEUP

SDS_TXD

CP_INT

PDA_ACTIVE

AT_RXD

SDS_RXD

SIMDATA

SIMCLK

PH_ACTIVE

DSP_IO

DSP_RWN

DSP_INT

TR_RST

CLK13M_TR

DSP_DB(12)

DSP_DB(13)

DSP_DB(14)

DSP_DB(15)

DSP_DB(2)

DSP_DB(3)

DSP_DB(4)

DSP_DB(5)

DSP_DB(6)

DSP_DB(7)

DSP_DB(8)

DSP_DB(9)

A(22)

CP_CSROMEN

CP_CSRAMEN

CP_WEN

CP_OEN

UPPER_BYTE

A(20)

A(3)

A(4)

A(5)

A(6)

A(7)

A(8)

A(9)

D(0)

D(1)

D(10)

D(11)

D(12)

D(13)

D(14)

D(15)

D(2)

D(3)

D(4)

D(5)

D(6)

D(7)

D(8)

D(9)

DSP_DB(0)

DSP_DB(1)

DSP_DB(10)

DSP_DB(11)

DSP_AB(0)

DSP_AB(1)

DSP_AB(2)

DSP_AB(3)

DSP_AB(4)

DSP_AB(5)

DSP_AB(6)

DSP_AB(7)

A(0)

A(1)

A(10)

A(11)

A(12)

A(13)

A(14)

A(15)

A(16)

A(17)

A(18)

A(19)

A(2)

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