RCA RDR3600V Manual de usuario
Communications Systems
RDR3600V
Service Manual
RCA Communications Systems
Circuit Description
一、 、 Frequencies constitute
The receiver uses secondary frequency conversion. The first IF is 49.95 MHz and the second IF is
450 kHz. The first local oscillation signal is provided by the PLL circuit.
The PLL circuit generates the required transmit frequency
as picture 1 Frequency structure
二、 、 Receiving department
Frequency structure of receiving department as picture 2
As picture 2 receiving department
1. The front-end (RF amplifier)
From the antenna signal into the transmit/receive switch diode circuits（D501，D503and D504）to
amplify.This signal passes through BPF (L508) and then enters mixing.These BPFs are adjusted by the
variable capacitors (D505, D506 and D512).The voltage of the input variable capacitor is adjusted by the
voltage output of the microprocessor (U301).
2. First mixer
The signal of the front end is mixed with the first local oscillator signal generated by the PLL
circuit at Q1 to generate a first intermediate frequency signal at a frequency of 49.95 MHz,and the
resulting signal is filtered by XF501
3. If amplifier circuit
The first intermediate frequency signal eliminates the signal of adjacent channel by crystal filter
(XF501) and amplifies the first frequency signal by the first intermediate frequency amplifier (Q507) and
enters the intermediate frequency system chip (U501).The IF system chip provides a second mixer, a second
local oscillator signal, a limiting amplifier, a quadrature detector, and an RSSI (Received Signal Strength
Indicator).The second mixer mixes the first intermediate frequency signal with a second local oscillation
signal output of 50.8 MHz and generates a second intermediate frequency signal of 400 MHz.
The second intermediate frequency signal continues to cancel the signal of the adjacent channel through
the ceramic filter (CF501).The filtered second intermediate frequency signal is amplified by a limiting
amplifier and demodulated by a quadrature detector with a ceramic discriminator (FD501). The demodulated
signal enters the audio power circuit.
4. wide / narrow switching circuit
Set the width and width of each channel by turning on the wide and narrow card switch.
When receiving WIDE (low level) data, Q511 connected.
When receiving NARROW (high) data, Q511 is disconnected.
Q511 is turned on / off with wide / narrow data, the U501 detector output level changes
frequently, with a constant output level that maintains a wide or narrow signal process.
as picture 3 Wide / narrow switching circuit
5. Audio amplifier circuit
The demodulated signal from U501 is sent to the audio amplifier via U102.The signal is output by AF
volume control and amplified by audio power amplifier (U204) to loudspeaker
6. Squelch
A part of the AF signal output by the U601 enters the IC, and the noise component is amplified and
modified by the filter and amplifier to generate the DC voltage corresponding to the noise level.The DC
signal is sent to the analog port (U301) of the microprocessor via the U261. U301 determines whether to
output sound from the speaker by detecting whether the input voltage is higher or lower than the preset
value.When the sound is output from the speaker, U301 sends a high level signal to the SP MUTE line and
turns on the U561.（as picture 4）
As picture 4 AFamplifier and squelch
7. Receive signaling
1) QT/DQT
The signal output by U601 enters microprocess (U301) through U201. U301 Determines whether QT or DQT
matches the set value, and controls the SP MUTE and speaker output sound based on this result
2) MSK（Fleet Sync）
The MSK input signal from the FM IC is sent to U201. The signal is mediated in the MSK mediator on
U201. The mediated data is sent to the CPU for processing.
3) DTMF
U601 DTMF output signal to U201. The decoded data has CPU processing.
三、 、 PLL frequency synthesis
The PLL circuit generates the first oscillation signal for reception and the RF signal for emission.
1. PLL
The frequency step of the circuit 5 or 6.25KHz.The output signal of the reference oscillator (VCO) of 16.8MHz is
amplified by Q605 buffer, and then divided by a programmable dual module counter in U601.The frequency division
signals are compared in the corresponding comparators of the U601.The generated signal is filtered through a low-pass
filter and transmitted to the VCO to control the oscillator frequency. (as picture 5)
2. VCO
The frequency used is generated by the Q601 in the transmit mode and is generated by Q603 in the receiving mode.
The oscillation frequency is controlled by feeding the VCO control voltage obtained from the phase comparator to the
shell diode (D607 and D608 in the mode of transmission, D602 and D605 in the reception mode).When receiving, the RX
pin is set to high, so that the Q602 is connected. At launch, the TX pin is set to high, amplifying the Q602 and
transmitting it to the RF amplifier.
as picture 5 PLL Circuit
3. Loss of lock detector
If the pulse signal appears on the PLD pin, a lockout occurs,The DC voltage obtained from C671, R623
and D601 lowers the input voltage of the microprocessor. The microprocessor detects this condition
after the launch is disabled, ignoring the PTT switch input signal.
4. Transmitter system
1) Microphone amplifier
The signal from the microphone passes through the U201. When the encoder is DTMF, the input signal of
the microphone is closed by U201. The signal is modulated by audio processing (U204), and then sent to VCO
modulation input.
as picture 6 Microphone amplifier
2) Drive and terminal amplifier
The signal from the VCO is amplified by the pre-driver amplifier (Q503) and the driver amplifier (Q502)
to 50mW.The output of the driver amplifier is amplified by the RF power amplifier (Q501) to 4.0W (1W at
low power). The RF power amplifier is composed of two MOSFETs. The output of the RF power amplifier is
connected by a harmonic filter (LPF) and an antenna switch ( D501) and sent to the antenna terminal.
3) Automatic power control (APC) circuit
The APC circuit monitors the current through the RF power amplifier (Q501) and keeps the current
stable. Changes in the current through the RF power amplifier cause the voltage drop of the R559, R560
and R561 to be sent to the differential amplifier U502A.U502B compares the output voltage of U502A from
the reference voltage of U301.U502B output voltage control RF power amplifier, drive amplifier, pre-drive
amplifier VG, so that the voltage remains the same.
High / low power changes are achieved by changing the reference voltage
502
301
as picture 7 Driver, terminal amplifier and APC circuit
5. Power Supply
The machine is powered by 3 5V power supplies to the microprocessor:5C,5R and 5T,At the same
time, when the power is switched on, a 3.3V keeps the output, although the 3.3V is often output,
but when the power is turned off, it is also turned off to prevent the microprocessor from
failure.
5C for the public 5V, in the non-power state to keep the output.
5R is the 5V used for reception and maintains output during reception.
5T is the 5V used for launch and remains output during launch.
6. control circuit
The control circuit is composed of microprocessor (U301) and external circuit. The main
functions of U301 are as follows:
a) a) According to the PTT input signal to convert and receive the state.
b) b) Read the system, group, frequency, and programming data from the memory circuit.
c) c) Send the frequency data to the PLL.
d) d) According to the squelch circuit output DC voltage to control the audio mute.
e) e) Control audio mute based on decoded data.
f) f) Launch Tone and programming data.
1) Frequency offset circuit
The microprocessor (U301) operates under the 8MHz clock. The oscillator has a circuit that can be converted
to U308 frequency.
If the "Beat Shift" is set to ON, the beat tone can be avoided.
302
as picture 8 Frequency offset circuit
2) Battery low voltage warning
The battery voltage is monitored by the microprocessor and a warning
tone is issued when the warning voltage is lower than the warning
voltage
a) The warning light flashes when the battery voltage is below 6.8V.
b) In the launch, when the battery voltage is below 5.8V, the handset
is forbidden to launch.
c) When the battery voltage drops to less than 5.3V, the hand held
machine.
7. Control system
Key and Channel Selector Circuit:
The keys and channel selector signals are input directly to the microprocessor.
Pin definition
Each pin is assigned as shown in chart 1.
chart 1---CPU pin definition:
Pin Type Name pin definition Description
1 O PE2 FLASH_CS Connect the serial FLASH to the first foot CS
2 O PE3 FLASH_SCLK/
LCD_DB6
Connect serial FLASH sixth pin SCK, multiplexing
to LCD_DB6
3 I PE4 FLASH_SDO Connect serial FLASH second pin SO
4 O PE5 FLASH_SDI/
LCD_DB7
Connect serial FLASH fifth foot SI, multiplexing
to LCD_DB7
5 O PE6 DMR_SLEEP
Connect HR_C5000 forty-seventh pin POWERDOWN; high level effective.
6 S VBAT VBAT Connect VDD with 0Ω resistor.
7 O PC13 TX_LED TX_LED control; active high.
8 O PC14 RX_LED RRX LED control; active high.
9 O PC15 LAMP Key backlight control, active high
10 S VSS_5 VSS_5 Connect VSSA.
11 S VDD_5 VDD_5 Connect 3.3V.
12 I OSC_IN OSC_IN Connect 8MHz crystal, 20pF capacitor ground.
13 O OSC_OUT OSC_OUT
With 0Ω resistor, connect 8MHz crystal, 20pF capacitor ground
14 I RESET RESET
Connect reset chip; active low. Reserved JTAG RESET
15 I PC0/EXTI0 TIME_SLOT_INTER Connect to HR_C5000 at 48 feet TIME_SLOT_INTER
16 I PC1/EXTI1 SYS_INTER Access to HR_C5000 pin 49 SYS_INTER
17 I PC2/EXTI2 RF_TX_INTER Connect to HR_C5000 at 50 feet RF_TX_INTER
18 I PC3/EXTI3/
AD123_IN13 RF_RX_INTER Connect HR_C5000 fifty-first foot RF_RX_INTER.
19 S VDD VDD Connect 3.3V.
20 S VSS VSS Connect VSSA
21 S VREF+ VREF+ Connect 3.3V.
22 S VDDA VDDA Connect 3.3V.
23 I PA0/
ADC123_IN0 MANDOWN MANDOWN input;
24 I PA1/
ADC123_IN1 BATT Battery voltage detection.
25 I PA2/
ADC123_IN2 QT/DQT_IN QT/DQT input;
26 I PA3/
ADC123_IN3 VOX VOX detection input
27 S VSS_4 VSS_4 Connect VSSA
28 S VDD_4 VDD_4 Connect 3.3V.
29 O PA4/ APC/TV
Transmit power control and receive tuned D / A outputs
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