Pro-Log 7701 Manual de usuario

STD

7000

7701

16K

Static

Ram

Memory

Card

USER'S

MANUAL

o

c

7701

16K Static Ram Memory Card

USER'S

MANUAL

10/81

.......

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hi.

, "

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iW4#4MA44QA

7701

16K

STATIC

RAM

MEMORY

CARD

USER~S

MANUAL

SECTION

2

SECTION

3

SECTION

4

SECTION

5

SECTION

6

SECTION

7

SECTION

8

SECTION

9

SECTION

10

APPENDIX

A

TAB

LEO

F

CON

TEN

T S

Data Sheet

Functional

Description

Card Address

Mapp

i,ng

Read,

Wri

te,

and

Bus

Control

Electrical

Spec

if

i

cat

ions

Mechanical

Specificqtions

2114 1024 x 4

Bit

Stat

icRam

Description

Schematic

Assemb

1y Drawing

Series 7000

Memory

Card Timing

Plan

#133

Thermal

Application

Note For

Microprocessor

Systems

Using STD/Series 7000 Cards

o

•

gp

u@@@

7701

~l(lc')

[~;)UJJ®~~~~~~~~--~-·-·:MEMORY

CARD

16K BYTE STATIC RAM

MEMORY CARD

This card provides sockets for

up

to

16,384 bytes

of

Read-Write

or

PROM Memory. The card uses 2114

type RAMs

or

equivalent and has sockets for

16

pairs

of

RAMs. Alternately the card

wi"

accept

3625

type PROMs

or

equivalent. PROMs and RAMs can

not

be mixed on the same card.

The

7701

decodes 16 address lines, and can

be

mapped into either 8K

or

16K bytes

of

consecutive

address space. An on-card jumper system allows

users

to

establish which 16K segment

of

a 64K

microprocessor memory each

7701

occupies.

FEATURES

• Sockets

for

16K bytes

of

2114L RAMs

or

3625

PROMs

• User selectable card address

•

All

STO BUS lines buffered

• Minimal

logic

bus loading

•

All

Ie's

socketed

• Single

+5V

operation

• Use Pro-Log 01004, 1Kx8 memories (two

2114L's)

II

3-STATE

BUS

DATA

BUS

Do-D7 I CONTROL

¢

Q4

MEMRQ"

RD"

WR"

MEMU"

ADDRESS

A13-A15

ADDRESS

A10-A12

ADDRESS

Ao-A.

),.

-READ

,.

WRITE -

CONTROL

~

-CARD

3/

SELECT

P-

DECODER

I l CHIP

1.0..

SELECT

r-

31 DECODER

,

101

BUF

I

11K STATIC RAM

SHADING INDICATES SOCKETS ONLY

$

i,e

liM'

au

= ...-

"\

11/

,

101

,

1

DATA

1/

,

RAM ARRAY

IK.I

""IW

DATA

~

r

~"E"

~

••

AV

IKd

-RIW

DATA HU

/

-Ill

'"

ADORE

II

/

7701

"INDICATES ACTIVE LOW LOGIC

2.

FUNCT10NAL

DESCRIPTION

The

7701

1s

organized

to

accept

16

pair

(32

sockets)

2114L 1024 x

4-bit

statis

RAMs.

'Although

the

card

may

be

populated

with

less

than

the

full

complement

of

21l4L

chips,

the

data

bus

drivers

are

enabled

anytime a

valid

address

is

present

even

if

memory

chips

are

not

plugged

in.

The

card

address

range

is

chosen

to

prevent

bus

contention

with

other

system

memory

elements

including

processor

on-card

memory,

other

memory

cards,

and

memory

mapped

I/O. Each pai r

of

the

211lll's

add 1K

8-b

it

bytes

of

RAM,

wh

ich

are

designated

memory

blocks

0 -15

(MBO

-

MB1S).

Each

memory

block

consists

of2

each (1024

x4)

2l14L

RAMs.

(Reference

Assembly Diagram 102687)

PROM

OPTION

;

\..

v11.)

""

~

(V

2..0:;:

..

-~~----~

________

1

r----.....-..--

.......

~---~

-

......

_-,

,

(v

I~)

,v,,~+

.

<VLlj

,

......

---

-

----~

r-

,-

----

--

.............

---.----.-. ----.

I

(VIi)

M

BS

(V2.~;

~---

-

------t

r-

--------~~

......................

-.j

,

(YI

S)

N\

~~

(\.t

l..l)

,

~---------

......

-----~.J

,

................

.-

.....

...-._

......

1

---

1

:

tUI'-)

M117

(V:l.4):

~-

-----..,.

v('

P (::

~

"-o"""~"

r---M"Bi

----,

~

LV

lS)

lU33)

:

..

---

-------4

.,

-

-----

-........----

--

..-

~

.-~,

'''\l~

f

(,

+

~~~)

_~J~_:J

1--'

--

..-.

~~

-

~

......

_,

'(\I

1.'1)

M

~

'0

(...J

as)

,

~

__________

...J

-,----...-...........

.........

-........-,

'l

V2.

~

")

M

~I

f

(v

~

(,)

:

..:---

-----"

:

(v

1..,) --:'Vll\

,2:

-;-37):

...

_

-_

-----_..J

r

-----

.........

-

--

.....

.-.....-

-----;

'lv

~~)

M &

'1

C'"

t

~)

;

.--

-

---

--------

,---

......

------~

.-

.......

-.

---.

.---_,

I(\J~\)

1V1I~J"\-

(v~q)

I

~-_,

____

~--l

r--------,

I

(U'l'l.)

~AB

1.5

(1I~~

I

~---.

-..J

\I

f~'~(\'

~C'.y~\\...

The

card

is

designed

to

accept

type

3625

PROMs

in

place

of

2114

RAMs

with

an

increase

in

card

power consumption.

PROMs

and

RAMs

may

not

be mixed

on

the

same

card.

If

this

option

is

exercised

be

sure

to

cut

traces

and ground

10

of

all

ch

ips.

2

o

IW4U!1j.ui\ly!n!!i'j!!

...

----.l_.~~

o

•

3.

CARD

ADDRESS

MAPPING

0000

3FFF

4000

7FFF

8000

BFFF

COOO

FFFF

o =

SX1~

(Lower

8K)

Sy~,:

(Upp'e

r

8K)

16K

BANKfl

=

SELECT

CARD

SELECT

~

ADDRESS

RANGE

'A'tsn4*

~

{

SO

0000"1

FFF

S1 2000

-t

3FFF

o 0 0

001

{

S2

4000 +5FFF

S3

6000~7FFF

o 1 0

o 1 1

{

S4

8000

+9FFF -

sx~'~

S5

AOOO

."BFFF

--Sy~;~

1 0 0

1 0 1

{

S6

COOO

-+DFFF

S7

EOOO

..,.

FFFF

1 1 0

1 1 1

CARD

SELECT

DECOD

I

NG

74LS42

(U4)

Lower

8K

Upper

8K

The

upper

three

(A15,

A14,

A13)

address

lines

are

decoded

by

an

74LS42

(U4)

for

card

address

selection.

A15

and

A14

are

decoded

to

select

one

of

the

four

16

banks. Address

line

A13

is

decoded

for

selection

of

the

lower

8K

(SX*)

and

the

upper

8K

(SV*)

of

the

16K

bank.

14-1...S+~

I'IIt"'~~@-~

D

(IJ~)

II

0-

16

} C

(:,'<>

'"

~.

f

I"Ff

AI5

,~

c.

s"

@

S5

~'4.@-~-.

'4,

.sc,...

&

~

()()<:)

""

~

f:~

t:

('S\\-ll'l'E~

POf:>I\loo-I~

S~

A1

3@-

IS

A

.$2..

S J

~o

3

} 'I-

<:)

~

»

'"]

1=1=='f.

J

o<::>~<:)...,

~\,<f'F

SY

*"

0PflE1<

~K

~t£eT\~

4-----.----;;

........

.s

X)t

LOw€R

cat<

s~LEc.·

..

noN

_==IM:",,,,,,·

41.

The

three

addres:s 1t'nes'

(A12~

All~

Ala)

are

decoded

by.

two

each

'74LS42,

U5and

U6,

U5

is

strobed

bY'

S.X"~

ltne

and

select~

the

lower

8 addres:s

banks.

u6

is

strobed

by

Sy*

line

a~d

sel~cts

the

upper

8

addres~

6ank~,

U5

and

U6

are

designated

Chi'p

Select

Decoders

on

the

s:chematt'c

dt'agram,

CHIP

5ELECr

DECODER~

AI\

AIO @-'---";:+--

SKlf

Each

chtp

enable

1

ine

goes

to

ptn

8

(cE~'~l

of

a

patr

of

2114L

chi'ps~p

(1

K

block)

The

lower

ten

address

1

ines

are

used

for

dlrect

address

lng

of

the

1K

chi'p

pat

rs,

and

are

buffered

bY'

U3

and U7.

4

o

c

FROM

CARD

SELECT

DECODER

SX~~

LOWER

8K

FROM

CARD

SELECT

DECODER

SY~':

LOWER

8K

(U6)

CHIP

ENABLE

CE

t;.K~':

CE2K~~

CE3K1:

CE4K~':

CE5K~~

CE6K*

CE7K~~

CE8K

(U5)

CHIP

ENABLE

CE9K~':

CE

I

OK~':

CE11~'~

CE12K~'~

CE

l3K~':

CE

14K~':

CEI5K~':

CE

l6K~':

5

CHI.P

~ET

UPPER

LOWE~

U9

Ul7

UIO

Ul8

U

11

U19

Ul2

U20

Ul3

U21

U14

U22

Ul5

U23

Ul6

u24

CH

I,

P

SET

UPPER

LOWER

U25 U33

U26

U34

U27

U35

u28

U36

U29 U37

U30

U38

U3l

U39

U32

u40

BLQCK

MBa

MBI

MB2

MB3

MB4

MB5

MB6

MB7

BLOCK

MB8

MB9

MBIO

MBlI

MBl2

MBl3

MBl4

MBl5

SH

I.

PPED

ADDRESS

RANGE

8000

-

83FF

8400

-

87FF

8800

-

8BFF

8coo

-

8FFF

9000

...

93FF

9400

-

97FF

9800

-

9BFF

9COO

...

9FFF

AOOO

-

A3FF

A400

-

A7FF

A800

-

ABFF

ACOO

-

AFFF

BOOO

...

B3FF

B400

-

B7FF

B800

-

BBFF

BCOO

...

BFFF

-------'---------------------------

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MEMORY

ADDRESS

MAP

&

JUMPER

SELECTION

TABLE

POR

lK

MEMORY

BLOCK

Card

Add,...

Selection o

6

4.

READ,

WRITE,

AND

BUS

CONTROL

o

,

Q.V

-S

~~

'f

f:-E.R S

?4L.S~~+

o'J

u2

~fMirt

~

L---------u

o 1 TO

WR\TE

EN~

wE*"

(p,~

\0)

($

MJ...

~\\A.\'-

(!,H-\P$

The

write

strobe

to

the

2114L chips.

qnd

the

read/wrrte

control

s(gnals

for

BUS

BUFFER

di

recttonql

control

is,

the

implementati"on

of

the

followi'ng Booleqn

Logic:

ROM;'·

=:

[(SX

+

Sy)

•

MERQ

•

READ]

WRM;'·::=

[(SX

+

Sy)

•

MERo.

•

WR

ITE]

If

Intel

Mask

ROM

3625

is

to

be

used,

It

is

necessary

to

cut

the

two

traces

of

the

WRM*

line

and ground

10

of

qllmemory

sockets!

Pads

qre

provided

for

this

option.

(PROMs.

and

RAMs

may

not

be

mixed

on

the

same

card).

NOTE:

The

Card's

data

bus

drivers

(74LS244)

Ul

and

U2

are

enabledanytlme

a

valid

address

is

present

even

if

memory

chips

qre

not

plugged

in.

The

card

address

range

is

chosen

to

prevent

bus

content

ion wi'th

other

system

memory

elements

including

processor

on-card

memory,

other

memory

cards,

and

memory

mapped

I/O.

7

, Ii';

«"

A

4M¥

4 4

1#;

M,

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