Pentek 7642 Manual de usuario
Page 2 Pentek Model 7642 Installation Manual
Warranty
Pentek warrants that all produ ts manufa tured by Pentek onform to published Pentek spe ifi ations and are free from defe ts in mate−
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servi e onditions for whi h they were furnished. The obligation of Pentek arising from a warranty laim shall be limited to repairing or
at its option, repla ing without harge, any produ t that in Pentek’s sole opinion proves to be defe tive within the s ope of the warranty.
Pentek must be notified in writing of the defe t or non onformity within the warranty period and the affe ted produ t returned to Pentek
within thirty days after dis overy of su h defe t or non onformity. Buyer shall prepay shipping harges, taxes, duties and insuran e for
produ ts returned to Pentek for warranty servi e. Pentek shall pay for the return of produ ts to buyer ex ept for produ ts returned from
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Pentek shall have no responsibility for any defe t or damage aused by improper installation, unauthorized modifi ation, misuse, negle t,
inadequate maintenan e, or a ident, or for any produ t that has been repaired or altered by anyone other than Pentek or its authorized
representatives.
The warranty des ribed above is buyer’s sole and ex lusive remedy and no other warranty, whether written or oral, is expressed or
implied. Pentek spe ifi ally dis laims fitness for a parti ular purpose. Under no ir umstan es shall Pentek be liable for any dire t, indi−
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Manual Revision History
Date Revision Comments
10/19/06 Preliminary Initial release.
2/5/07
to
9/30/08
Se t 1.15, updated Power Spe ifi ations.
or Rev C boards: Se t 2.2, added jumper blo k JB2, PCI Bus Mode. Se t 2.2.1 orre ted jumper JB1 fa tory
default settings. New Se t 7.4, added des ription of ADC to DDR Memory data pa king. Se t 1.15, orre ted
Analog Signal oupling to AC per KBCase 1320. Table 2−7 reversed differential P/N for ea h signal pair per
KBCase 1321. Se t 4.7, added Figure 4−5 timing delays. Se t 1.6, 1.15, 4.3, 6.12 added Option 101, DAC5687.
Se t 1.15, orre ted input lo k spe to ‘1 to 300 MHz’. Se t 4.4, orre ted DAC FIFO size.
or 7142 boards with PCI7142 revision date of 10/01/07 or greater:
Se t 4.5.5, 5.7.3, 5.21, 5.22, 5.23, added FPGA Load DMA des ription & registers. Se t 1.4, introdu ed new
FPGA terms: PCI FPGA (XC4VFX60) & Signal FPGA (XC4VSX55). Se t 1.12, updated baseline FPGA usage
per entages. Moved Vendor Data Sheets to separate do ument, 809.7x420. Se t 6.14.2, reversed BAR2
addresses of User In/Out FIFOs. Added Option 100, XC4VFX100 (PCI) FPGA, & Option 110, XC4VLX100 (Sig−
nal) FPGA. Se t 2.3, orre ted Pentek part # for JTAG PCB to 004.71402. Se t 2.6.1, orre ted full s ale input to
+10 dBm. Se t 1.15, hanged size spe s to PCI ard size. Se t 5.4, orre ted register BAR addresses.
11/19/08 A Manual released, Revision A
2/6/09 B Changed to Installation Manual, refer to 800.71420 for Operating Manual.
7/2/09 B.1 Se t 2.5.3, orre ted GND pins, should be B31 not B32.
Printed in the United States of Ameri a.
Pentek Model 7642 Installation Manual Page 3
Page
Table of Contents
Rev.: B
Chapter 1: Introduction
1.1 General Description..............................................................................................................................5
1.2 Features ..................................................................................................................................................5
1.3 Model 7642 Documentation ................................................................................................................5
1.4 Block Diagram.......................................................................................................................................6
igure 1−1: Model 7642 Block Diagram...........................................................................................6
1.5 Principle of peration..........................................................................................................................7
1.6 Specifications.........................................................................................................................................8
Chapter 2: Installation and Connections
2.1 Inspection...............................................................................................................................................9
igure 2−1: Model 7642 Assembly....................................................................................................9
2.2 Jumper and Switch Settings ..............................................................................................................10
2.2.1 Removing PMC Module from PCI Adapter .................................................................11
igure 2−2: Removing PMC Module from PMC Adapter ........................................11
2.2.2 Replacing PMC Module onto PCI Adapter ..................................................................12
igure 2−3: PCI Adapter PMC Connections ................................................................12
2.2.3 7142 PMC Module Jumpers ............................................................................................13
igure 2−4: Model 7142 PCB Assembly Drawing, Component Side......................13
Table 2−1: actory Default Jumpers..............................................................................13
2.2.4 PMC to PCI Adapter Switches ........................................................................................14
igure 2−5: PMC to PCI Adapter, Component Side ..................................................14
Table 2−2: PCI Adapter Switch Settings......................................................................15
2.3 Installing the Pentek JTAG PC Assembly.......................................................................................16
igure 2−6: Model 7642 − JTAG PC Assembly Mounting.........................................................16
2.3.1 JTAG J2 Connector ...........................................................................................................17
Table 2−3: JTAG J2 Connector .......................................................................................17
2.3.2 JTAG J3 Connector ...........................................................................................................17
Table 2−4: JTAG J3 Connector .......................................................................................17
2.4 Installing the Model 7642 in a Personal Computer .......................................................................18
igure 2−7: Model 7642 Mounted in PCI Slot ..............................................................................19
2.5 PCI Adapter Connectors....................................................................................................................20
2.5.1 Power Connector ..............................................................................................................20
2.5.2 JTAG Connector ................................................................................................................20
Table 2−5: JTAG JP8 Connector.....................................................................................20
2.5.3 PCI FPGA I/ Connections ( ption 104) .....................................................................21
Table 2−6: Option 104 PCI PGA I/O Pin Connections ............................................22
2.6 PCI Adapter LEDs ..............................................................................................................................23
Table 2−7: PCI Adapter LEDs..........................................................................................................23
Page 4 Pentek Model 7642 Installation Manual
Page
Table of Contents
Rev.: B
Chapter 2: Installation and Connections
2.7 Front Panel Connections ................................................................................................................... 24
igure 2−8: 7642 PMC ront Panel ................................................................................................ 24
2.7.1 Analog Input Connectors ................................................................................................ 24
2.7.2 Clock Input Connector .................................................................................................... 24
2.7.3 Analog utput Connector .............................................................................................. 24
2.7.4 SYNC/GATE Connector ................................................................................................. 25
Table 2−8: SYNC/GATE Connector Pins..................................................................... 25
2.8 Front Panel LEDs................................................................................................................................ 26
2.8.1 Master LEDs ...................................................................................................................... 26
2.8.2 Terminate LEDs ................................................................................................................ 26
2.8.3 ver Temperature LED ................................................................................................... 26
2.8.4 Clock LEDs ........................................................................................................................ 26
2.8.5 verload LEDs ................................................................................................................. 26
Pentek Model 7642 Installation Manual Page 5
Rev.: B
Chapter 1: Introduction
1.1 General Description
The Pentek Model 7642 is a multichannel, high−speed data conve te suitable fo con−
nection to HF o IF po ts of a communications system. Using the PCI Ca d module fo −
mat, it includes fou A/D conve te s and one D/A conve te capable of bandwidths to
40 MHz and above.
The Model 7642 consist of one multichannel t ansceive 7142 PMC (PCI Mezzanine
Ca d) module mounted on a PCI adapte boa d, assembled and tested as a single PCI
boa d. It it eady to plug into compute boa ds with PCI bus slots.
1.2 Features
!Fou 125−MHz, 14−bit A/D conve te s
!One digital upconve te with one 500−MSPS, 16−bit D/A conve te
!768 MBytes of DDR2 SDRAM
!Xilinx® Vi tex™−4 FPGAs
!Up to 2.0 seconds of delay o data captu e at 100 MHz
!Dual timing buses fo independent input and output clock ates
!LVDS clock/sync bus fo multi−module synch onization
!32 pai s of LVDS connections to the Vi tex−4 FPGA fo custom I/O on P4
1.3 Model 7642 Documentation
This Model 7642 Ope ating Manual desc ibes the installation and connections fo the
7642 PCI assembly. Documentation of the 7142 PMC ope ation and p og amming is
p ovided in the supplied Model 7142 Ope ating Manual, Pentek document #800.71420.
NOTE: When the 7142 PMC is installed on the PMC to PCI adapte , the following
featu es identified in the 7142 Ope ating Manual a e not available.
• VITA 42.0 XMC compatible with switched fab ic inte faces (Option 5xx)
Datasheets fo the p og ammable devices on the Model 7642 a e p ovided in the Pentek
Model 7x42 Se ies Supplemental Manual, pa t numbe 809.7x420. This document is
available on the CD p ovided by Pentek, in file 8097x420.pdf (PDF fo mat).
Page 6 Pentek Model 7642 Installation Manual
Rev.: B
1.4 Block Diagram
The following is a simplified block diagram of the Model 7642 digital receiver.
The following defines the different uses of the term ‘Channel’ in this manual (refer also
to the block diagram above).
•Analog Input Channels — There are four analog input channels, one for each
analog RF input, identified as A/D 1, A/D 2, A/D 3, and A/D 4, corresponding to
the RF inputs labeled CH 1 IN, CH2 IN, CH3 IN, and CH 4 IN on the front panel.
•Analog Output Channel — There is one digital upconverter output channel for the
DAC5686, identified as DAC, corresponding to the RF output labeled DAC UT on
the front panel.
TIMING BUS
GENERATOR A
TTL Gate/
Trigger
XTL
OSC.
SYNC
INTERRUPTS
& CONTROL
Control/
Statu
PCI BUS (64 Bits 66 MHz)
FPGA I/O
(Option 104)
Sync Bu B
XTL
OSC.
LVDS Clock A
LVDS Sync A
LVDS Gate A
LVDS Clock B
LVDS Sync B
LVDS Gate B
TTL Sync
Sync Bu A
DDR
SDRAM
64M x 32
DDR
SDRAM
64M x 32
DDR
SDRAM
64M x 32
64
32 32 32
CH 1
RF IN
CH 2
RF IN
LTC2255 #1
14−BIT A/D
LTC2255 #2
14−BIT A/D
RF
XFORMER
14 14
RF
XFORMER
A/D 1
DAC
OUT
RF
TRANSFORMER
DAC5686
16−BIT D/A & DUC
32
A/D 2
CH 3
RF IN
LTC2255 #3
14−BIT A/D
14
RF
XFORMER
A/D 3
CH 4
RF IN
LTC2255 #4
14−BIT A/D
14
RF
XFORMER
A/D 4
64
DAC
To All Section
EXT
CLK
TIMING BUS
GENERATOR B
Virtex−4 XC4VSX55 or XC4VLX100 FPGA
64
Virtex−4 XC4VFX60 or
XC4VFX100 FPGA
LOCAL
BUS 32 32 32 HI−SPEED
BUSES
PCI 2.2
INTERFACE
Figure 1−1: Model 7642 Block Diagram
Pentek Model 7642 Installation Manual Page 7
Rev.: B
1.5 Principle of Operation
The Model 7642 is a complete software radio transceiver suitable for direct connection
to HF or IF ports of a communications system. Using the popular PCI board format, it
includes four A/D and one D/A converters.
The 7642 features a Xilinx® Virtex−4 XC4VSX55 FPGA (XC4VLX100 with ption 110)
and a Xilinx Virtex−4 XC4VFX60 FPGA (XC4VFX100 with ption 100). The XC4VSX55
(or XC4VLX100) FPGA, identified as the “Signal FPGA” in this manual, can be pre−
configured with one of a variety of optional IP cores to provide signal translation, pro−
cessing, and time delay functions. In addition to pre−configured functions, user−cre−
ated FPGA programming is supported by Pentek's GateFlow® Designer's Kit, Model
4953 ption 142. The XC4VFX60 (or XC4VFX100) FPGA, identified as the “PCI FPGA”
in this manual, provides board interfaces including PCI. PCI FPGA I/ connections
are provided through the optional PMC P4 connector ( ption 104).
The 7642 includes a large 768−MByte block of DDR2 SDRAM. This memory is con−
trolled by the Signal FPGA and is organized as three 256−MByte banks, 32 Mbyte deep
by 32 bits wide. Separate banks (separate address and data per bank) allow simulta−
neous access to all banks. This memory can be used as buffer memory when transfer−
ring data between board resource or to off−board resources.
Four A/D converters provide input to a Signal FPGA, where the data can be formatted,
processed or routed to board resources.
The D/A converter includes both interpolation filters and an upconverter stage capable
of producing baseband I & Q and quadrature modulation analog output.
The 7642 includes dual onboard crystal oscillators for clocking, but can also accept
external clocks through a front panel MMCX connector. The 7642 is equipped with a
dual LVDS front panel clock and sync bus that can synchronize up to eight modules
with built−in master/termination functions. The bus format is compatible with other
Pentek PMC modules and will work with the Model 9190 Clock and Sync Distribution
Amplifier for synchronizing up to 80 modules.
Page 8 Pentek Model 7642 Installation Manual
Rev.: B
1.6 Specifications
Signal Processing
Refer to the Model 7142 perating Manual, Pentek document #800.71420
PMC to PCI Adapter
Device: Technobox™ Model 5012
PCI Bridge: Intel 31154
PCI Bus Interface: 32 or 64 bit, PCI 33/66 MHz, PCI−X 33/66/100/133 MHz
PMC Interface: 32/64 bit, 33/66/100 MHz
Estimated Power Consumption
PCI Adapter
With no PMC: (TBD)
7142 PMC:
Current Draw: +3.3V +5V +12V −12V
1.35A 2.5A 0.2A * NC
* 12V only connected to voltage test circuit
PMC Power: 16.95 Watts
Note: Power estimated with FPGA base circuitry. Power consumption increases
when custom user FPGA designs are added. Different aspects of the FPGA
design contribute to power consumption such as clock speed, number of logic
slices used, number of DSP multipliers used, and amount of block RAM used.
Physical
Dimensions: Standard PCI card
Depth: 149.0 mm (5.87 in)
Height: 76.2 mm (3.0 in)
Weight:
PCI Adapter (TBD)
7150 PMC 127.6 grams (4.5 oz)
Pentek Model 7642 Installation Manual Page 9
Rev.: B
Chapter 2: Installation and Connections
2.1 Inspection
After unpacking, inspect the unit carefully for possible damage to connectors or com−
ponents. If any damage is discovered, contact Pentek immediately at (201) 818−5900.
Please save the shipping container and packing material in case reshipment is required.
The following figure illustrates the complete Model 7642 assembly as shipped, with the
7142 PMC module mounted onto the PMC to PCI adapter.
PMC to PCI
dapter
PCI Bus Connectors
PCI
Slot
Panel
7142 PMC Module
Power
Connector
96−pin DIN
Connector
Dip
Switches
Figure 2−1: Model 7642 ssembly
Page 10 Pentek Model 7642 Installation Manual
Rev.: B
2.2 Jumper and Switch Settings
The following subsections cover user operating parameters that are set by shorting
jumpers or dip switches on the Model 7642.
The term jumper (or jumper block) refers to a group of two or more pins on a circuit
board that may be connected in pairs by a shorting jumper to set or change an operat−
ing characteristic of the board. A pair of pins connected in this manner are referred to
as installed, or shorted. A pair of pins that are not connected are called removed, or
open. The shorting jumpers used on the Model 7642 are for 0.020" (0.51 mm) square
pins spaced on 0.079" (2.00 mm) centers. These jumpers are DuPont™ part number
86730−001, or equivalent. Pentek’s part number for these jumpers is 356.00010.
As shipped from the factory, several jumpers are installed in default positions on your
board. The default operating parameters they select may or may not meet your
requirements. Before installing your Model 7642, please review the following subsec−
tions to determine whether you need to change any of these settings.
The Model 7642 assembly consists of two modules, a Pentek 7142 PMC module and a
PMC to PCI adapter board (Technobox™ Model 5012). See Section 2.2.4 for description
of the jumper settings on the 3674 PCI adapter board.
As shipped, the 7142 PMC module is mounted onto the PCI adapter. Note that all
jumpers on the PMC are located on the component side of the PMC, and are not acces−
sible in this shipped configuration. See Section 2.2.3 for the jumper settings for the 7142
PMC. If you need to access this jumper on the 7142 PMC, you must first remove the
PMC module from the PCI adapter board, as described in Section 2.2.1.
Note
The user should not change jumpers or switches not described in this
chapter—those are reserved for factory test and setup purposes only.
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