ON Semiconductor A5191HRTNGEVB Manual de usuario

©Semiconductor Components Industries, LLC, 2016

July, 2016 − Rev. 5 1Publication Order Number:

EVBUM2130/D

A5191HRTNGEVB

Evaluation Board User's

Manual

Introduction

The A5191HRTNGEVB evaluation board includes all

external components needed for operating the

A5191HRT IC and demonstrates the small PCB surface area

such an implementation requires. The EVB allows easy

design of HART®implementations using A5191HRT.

Overview

The A5191HRT is a single−chip, CMOS modem for use

in highway addressable remote transducer (HART) field

instruments and masters. The modem and a few external

passive components provide all of the functions needed to

satisfy HART physical layer requirements including

modulation, demodulation, receive filtering, carrier detect,

and transmit−signal shaping.

The A5191HRT uses phase continuous frequency shift

keying (FSK) at 1200 bits per second. To conserve power the

receive circuits are disabled during transmit operations and

vice versa. This provides the half−duplex operation used in

HART communications.

Features

•Single−chip, Half−duplex 1200 Bits per Second FSK

Modem

•Bell 202 Shift Frequencies of 1200 Hz and 2200 Hz

•3.0 V − 5.5 V Power Supply

•Transmit−signal Wave Shaping

•Receive Band−pass Filter

•Low Power: Optimal for Intrinsically Safe Applications

•Compatible with 3.3 V or 5 V Microcontroller

•Internal Oscillator Requires 460.8 kHz Crystal or

Ceramic Resonator

•Meets HART Physical Layer Requirements

•Industrial Temperature Range of −40°C to +85°C

•Available in 28−pin PLCC, 32−pin QFN and 32−pin

LQFP Packages

Applications

•HART Multiplexers

•HART Modem Interfaces

•4 – 20 mA Loop Powered Transmitters

Figure 1. A5191HRTNGEVB Evaluation Board

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EVAL BOARD USER’S MANUAL

A5191HRTNGEVB

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ELECTRICAL CHARACTERISTICS

Table 1. ELECTRICAL CHARACTERISTICS OF THE A5191HRTNGEVB BOARD

Symbol Parameter / Condition

Value

Unit

Min Typ Max

VDD Supply voltage 2.78 3 6.00 V

CURRENT CONSUMPTION

IDD VDD = 2.78V, idle 417 mA

IDD VDD = 3.00 V, idle 420 mA

IDD VDD = 6.00V, idle 780 mA

IDD External clock, VDD = 3.00 V, idle 350 mA

TRANSMITTED FREQUENCY

fMMark “1” 1197 Hz

fSSpace “0” 2194 Hz

LEVELS

VTxA Amplitude Transmit Output 500 mVpp

VCD Carrier Detect Level 110 mVpp

REFERENCE VOLTAGES

VAREF AREF 1.212 V

VCDREF CDREF 1.128 V

A5191HRT DESCRIPTION

The A5191HRT modem is a single−chip CMOS modem

for use in HART field instruments and masters. It includes

on−chip oscillator and a modulator and demodulator module

communicating with a UART without internal buffer. The

A5191HRT requires some external filter components and a

460.8 kHz clock source. This clock source can either be the

interface oscillator by using a crystal or ceramic resonator,

or an external clock signal.

When the device is transmitting data, the receive module

is shut down and vice versa to conserve power. With simple

power−saving maneuvers, the IC can be made to operate

with a current consumption of as little as 250 mA. For more

information related to this subject see the application note

AND9030 “A5191HRT Design for Low−Power

Environments”.

TEST AND MEASUREMENT TOOLS

Listed below are the tools used to acquire the values presented in this Evaluation Board User’s Manual.

•Oscilloscope Tektronix DPO4034 350 MHz

•Signal Generator Agilent 33120A

•Network Analyzer AP Instruments 300

A5191HRTNGEVB

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A5191HRTNGEVB DESCRIPTION

Schematic Diagram

Figure 2. Schematic of A5191HRTNEVB

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BOM List

Table 2. A5191HRTNEVB BILL OF MATERIALS

Quantity Reference Value; Size Manufacturer & Comments

4C1, C2, C4, C6 100 nF, 0603

3C3, C5, C7 220 pF, 0603

2C8, C9 1 nF, 0603

2C10, C11 470 pF, 0603

3FB1, FB2, FB3 600Z, 0805

3IDC1, IDC2, IDC3 0.1” header, 10 pin

1 J1 Barrel connector Not populated

1 J2 SMB connector Not populated

4R1, R2, R6, R21 200k, 0603

1 R3 0R, 0603

2R4, R11 14k7, 0603

2R7, R14 499k, 0603

3R8, R16, R17 215k, 0603

1 R12 1k, 0603

1 R10 422k, 0603

1 R13 3M, 0603

1 R15 787k, 0603

1 R18 24k, 0603

1 R20 DNP, 0603 Not populated

1 U1 CAT808NTDI−27GT3 ON Semiconductor

1 U2 A5191HRT ON Semiconductor

1 U3 TLV431ASNT1G ON Semiconductor

1 Y1 460.8 kHz ECS Crystal ZTBF−460.8−E

General Overview

The A5191HRTNGEVB evaluation board demonstrates

the external components required for the operation of the IC.

We will cover the different sections below as well as possible

alternatives. A drawing of the board where the different

sections are indicated is shown below.

Figure 3. Board Drawing With Indication of Different Sections

A5191HRTNGEVB

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Power Supply and References

Power Supply

Figure 4. Supply Voltage and Power on Reset

The A5191HRTNGEVB is designed for a nominal

voltage of 3 V. However, A5191HRT can be operated up to

6 V. For optimal functioning of the board, the values of

several resistors should be changed for operation at voltages

higher than 3 V. See the sections on reference voltages and

bias for more information on this.

Current consumption of the module is very limited,

making it ideal to be battery or loop−powered.

Measurements of the power consumption of the module are

listed in Table 3.

Table 3. MODULE CURRENT CONSUMPTION

Symbol Condition Current Consumption

IDD VDD = 2.78 V, Transmit 428 mA

IDD VDD = 2.78 V, Receive 417 mA

IDD VDD = 3 V, Transmit 443 mA

IDD VDD = 3 V, Receive 419 mA

IDD VDD = 6 V, Transmit 837 mA

IDD VDD = 6 V, Receive 781 mA

IDD VDD = 3 V, Transmit, Ext. Osc. 362 mA

IDD VDD = 3 V, Receive, Ext. Osc. 350 mA

The module will use less power when clock signal is

applied externally, as this allows the modem to shut down

the oscillator circuit. As is to be expected, a higher supply

voltage increases current consumption.

It is advised to use a voltage supervisor such as CAT808

to prevent the modem to begin operation when the supply

voltage is not yet reliable. This will guarantee correct

operation of the digital circuitry.

The voltage supervisor will keep the RESETB pin low

until its threshold value is reached (2.7 V on the

A5191HRTNGEVB). This ensures that some time has

passed after the supply voltage reaches the turn−on voltage

level of 2.5 V.

The RESETB and VDD pin signals during startup are

shown in Figure 5. The measured start−up delay is 2.6 ms.

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Figure 5. Power and RESETB Waveform During Startup, Showing 2.63 ms Startup Delay

C1, C2 and C6 are 100 nF ceramic decoupling capacitors

located directly adjacent to each power pin. For analog

power pins, an additional large−value ceramic capacitor

may be needed in addition to the 100 nF decoupling

capacitor when the application is intended for high−noise

environments.

For loop powered devices, additional decoupling with a

large value capacitor is advised to prevent digital noise from

being transmitted on the current loop.

The ferrite beads FB1, FB2 and FB3 in series with power

supply lines help to reduce EMI.

Reference voltages and comparator bias

A5191HRT needs an external analog reference voltage

for the receiver or demodulator (RX) comparator and carrier

detect (CD).

The AREF reference voltage sets the trip point of the

demodulation operational amplifier of the 5191HRT. The

AREF reference voltage is also used in setting the DC

operating point of the received signal after it has passed

through the band−pass receive filter. The ideal value for the

AREF reference voltage depends on the voltage supply, and

is chosen roughly half−way the operating range of the

operational amplifiers. This ensures the range of the

operational amplifier is maximized. For operation at 3 V, a

1.24 V reference voltage is recommended. For operation at

5 V, a 2.5 V reference voltage is recommended.

For A5191HRTNGEVB, the TLV431 shunt regulator is

used with an internal reference of 1.24 V. This reference is

compared against the output voltage, and the shunt transistor

base is adjusted until it sinks enough current to drop the

output to 1.24 V.

A simple low pass filter formed by R12 and C11 is added

to increase reference stability. A slight voltage drop is

observed over this filter caused by loading of the reference

voltage. However, the voltage drop and the influence on the

operation of the IC is minimal. Measurements show a

voltage drop of 22 mV over R12, indicating a current of 22

mA. Of this current ca. 5 mA is consumed by the CDREF

resistor division. The rest (ca. 17 mA) is used internally by

the IC through the AREF pin. Current consumption through

the CDREF pin is negligible.

The CDREF reference voltage sets the threshold for the

carrier detect comparator. As the received signal is biased at

AREF, the difference between CDREF and AREF will

determine the minimum amplitude needed for the carrier

detect comparator to flip. A (AREF−CDREF) of 80 mV

corresponds to signal of approximately 100 mV

peak−to−peak at the input of the receive filter. The CDREF

reference voltage on the A5191HRTNGEVB is generated

by a resistor division of the AREF reference. This will create

an extra load on the low pass filter of AREF. However, the

drop on the resistor of the low pass can be considered

negligible.

An external resistor is required to set the bias current. The

voltage over the bias resistor is regulated to AREF, so that

the resistor determines a bias current. This bias current

A5191HRTNGEVB

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controls the operating parameters of the internal operational

amplifiers and comparators and should be set to

approximately 2.5 mA. A bias resistor of 499 kWis used on

the A5191HRTNGEVB. For low cost solutions, a 470 kWis

acceptable with minimal effect on operation.

Table 4. REFERENCE VOLTAGES

Description Value

AREF reference voltage 1.212 V

CDREF reference voltage 1.128 V

Current through R12 22 mA

Figure 6. Reference Voltages Schematic

Clock Generation

A5191HRT is operated on a 460.8 kHz clock signal. The

A5191HRTNGEVB has two options for providing this

clock signal. The first method is by using a ceramic

resonator or a crystal, for example ECS Crystal

ZTBF−460.8−E ceramic resonator, loaded with two 220 pF

capacitors.

Alternatively, a clock signal can be provided externally

when R3 is removed and C3 is replaced by a resistor of 0 W.

This signal can be provided by a microcontroller or any other

external oscillator circuit. The module uses less power when

clock signal is applied externally, as this allows the modem

to shut down the oscillator circuit. A typical current

consumption witnessed by utilizing an external oscillator is

70 − 100 mA less. However, care must be taken that this

external signal has the required accuracy (1%).

Duty cycle of the clock signal is specified between 40%

and 60%. No errors were observed during testing in

operation between 20% and 80% duty cycle. However,

operation on such very small or very large duty cycle is not

recommended, due to the possibility of timing errors that

may occur under specific circumstances (including, but not

limited to, temperature variations).

Figure 7. Clock Generation Circuit

a.) Resonator Option b.) External Clock Option

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Microcontroller Interface IDC1

RESET

RxD

TxD

RTS

IDC1

VCC

R23

PC20110513.4

Figure 8. Microcontroller Interface

Table 5. MICROCONTROLLER INTERFACE

Pin Number Signal Type Description

1 RST Open drain Reset signal from the voltage supervisor, open drain with pull−up

3 CD Output Carrier Detect

5 RxD Input Receive from microcontroller

7 TxD Output Transmit towards microcontroller

9 RTSB Input Request to send

2, 10 VDD Power 3 V nominal

4, 6, 8 GND Power

The interface towards a microcontroller is provided in

IDC1. This interface can also be used to supply power to the

module. The nominal supply voltage for the module is 3 V.

For more information see the section on power supply and

references.

The RESETB line to the modem is an open drain signal.

A pull−up resistor of 200 kWis provided on the board, and

should not be duplicated on the microcontroller side. The

reset signal is generated on the board, and could be used as

reset signal for other IC such as the microcontroller.

The CD signal rises when a HART signal of ca. 100 mVpp

is detected on the current loop. See the section on reference

voltages for more information on these threshold level

settings. When no signal, or a signal of limited amplitude is

present, the CD line is pulled down to 0 V.

The RxD, TxD, and RTSB signals implement a standard

UART interface at 1200 baud with start bit 8 data bits, parity

bit and stop bit (11−bit frame). The RTSB signal disconnects

the transmitter circuit when pulled high, and should be held

low before any data is transmitted. Data frames are not

buffered by the modem. Instead, data is transmitted bit by

bit. Care should be taken to avoid clock skew in the receiving

UART. If the same time base is used for both the modem and

the UART, a 1% accurate time base may not be sufficient.

The problem is a combination of receive data jitter and clock

skew between transmitting and receiving HART devices. If

the transmit time base is at 99% of nominal and the receive

time base in another device is at 101% of nominal, the

receive data (at the receiving UART) will be skewed by

roughly 21% of one bit time at the end of each 11−bit byte.

This is shown in Figure 9. The skew time is measured from

the initial falling edge of the start bit to the center of the 11th

bit cell. This 21% skew by itself is a relatively good result.

However, there is another error source for bit boundary jitter.

The Phase Lock Loop demodulator in the A5191HRT

produces jitter in the receive data that can be as large as 12%

of a bit time. Therefore, a bit boundary can be shifted by as

much as 24% of a bit time relative to its ideal location based

on the start−bit transition. (The start−bit transition and a later

transition can be shifted in opposite directions for a total of

24%.)

The clock skew and jitter added together is 45%, which is

the amount that a bit boundary could be shifted from its

expected position. UARTs that sample at mid−bit will not be

affected. However, there are UARTs that take multiple

samples during each bit to try to improve on error

performance. These UARTs may not be satisfactory,

depending on how close the samples are to each other, and

how samples are interpreted. A UART that takes a majority

vote of three samples is acceptable.

A5191HRTNGEVB

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Figure 9. Clock Skew

Even if your own time base is perfect, you still must plan

on a possible 35% shift in a bit boundary, since you don’t

have control over time bases in other HART devices.

Transmitter

The TxA modem pin is decoupled through a 100 nF

capacitor to pin 7 of IDC2. For certain applications, it might

be required to remove this capacitor and replace it by a 0 W

resistor. The output on this pin is a 500 mVpp signal

trapezoid waveform shown in Figures 10 and 11. This pin

can only drive impedances higher than 30 kW, and as a

consequence may need to be amplified to drive low

impedances. For a given implementation of a master or

slave, it may be required to remove C4 and replace it with a

0 Wresistor to allow the decoupling to occur elsewhere in

the master implementation.

The nominal frequency of the output is 1196.9 Hz for

“mark” and 2194.3 Hz for “space”. These frequencies are

dependent on the accuracy of the A5191 clock.

Figure 10. Output Waveform (Mark)

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Figure 11. Output Waveform (Space)

Receiver

The receive band pass filter is implemented on the

A5191HRTNGEVB. The values are listed in Table 6 and the

filter schematic is displayed in Figure 12. For cost purposes,

this filter can be implemented using E12 value resistors with

minimal changes to the filter characteristic. This

implementation will have a slightly reduced gain in the pass

band.

Figure 12. Receive Filter

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