OLIMEX LPC-E2468 Manual de usuario

LPC-E2468 development board

Users Manual

Rev.B, Februar 2008

INTRODUCTION:

LPC-E2468 uC Linux development prototype board with LPC2468 USB

Ethernet SD/MMC in credit card format.

BOARD FEATURES:

-MCU: LPC2468;

- 16MB SDRAM;

- 128 MB NAN Flash;

- standard JTAG connector with ARM 2x10 pin layout for

programming/debugging with ARM-JTAG;

- Ethernet 100MBit;

- 2x USB hosts;

- USB-to-RS232 converter device connected to LPC2468 UART;

- SD/MMC card connector;

- UEXT connector with I2C SPI RS232 and power supply for

connecting add-on modules like RF link MP3 etc available from

Olimex;

- trimpot connected to ADC;

- RESET circuit with external control of Philips ISP utility via RS232

port;

- two USER button;

- RESET Button;

- two on board voltage regulators 3V and 5V with up to 800mA

current;

- Extension port connector for many of microcontrollers pins;

- single power supply: External power supply USB or JTAG connector;

- Battery holder and connector for the RTC;

- power supply led;

- FR-4 1.5 mm red soldermask component print;

- Dimensions: 90x60mm (3.54 x 2.36").

ELECTROSTATIC WARNING:

The LPC-E2468 development board is shipped in protective anti-static

packaging. The board must not be subject to high electrostatic potentials.

General practice for working with static sensitive devices should be applied

when working with this board.

BOARD USE REQUIREMENTS:

Cables: USB A-B cable to connect to virtual serial port on the board.

You will need LPT cable if you want to program the MCU with

AVR-JTAG. You might need other cables in case of other

programmers/debuggers.

Hardware: Programmer/debugger AVR-JTAG or any compatible tool.

Software: The board is delivered with uC Linux pre-loaded. You could

develop projects for the board with Eclipse IAR etc. Please

refer to the LPC-E2468 Quickstart Guide which is on the CD

for more details on the software requirements.

PROCESSOR FEATURES:

The LPC2468 processor has the following features:

● ARM7TDMI-S processor running at up to 72 MHz.

● 512 kB on-chip flash program memory with In-System Programming

(ISP) and In-Application Programming (IAP) capabilities. Flash

program memory is on the ARM local bus for high performance CPU

access.

● 98 kB on-chip SRAM includes:

▬64 kB of SRAM on the ARM local bus for high performance CPU

access.

▬16 kB SRAM for Ethernet interface. Can also be used as

general purpose SRAM.

▬16 kB SRAM for general purpose DMA use also accessible by

the USB.

▬2 kB SRAM data storage powered from the Real-Time Clock

(RTC) power domain.

● Dual Advanced High-performance Bus (AHB) system allows

simultaneous Ethernet DMA USB DMA and program execution

from on-chip flash with no contention.

● EMC provides support for asynchronous static memory devices such

as RAM ROM and flash as well as dynamic memories such as

Single Data Rate SDRAM.

● Advanced Vectored Interrupt Controller (VIC) supporting up to 32

vectored interrupts.

● General Purpose AHB DMA controller (GPDMA) that can be used

with the SSP

● I2S-bus and SD/MMC interface as well as for memory-to-memory

transfers.

● Serial Interfaces:

▬Ethernet MAC with MII/RMII interface and associated DMA

controller. These functions reside on an independent AHB bus.

▬USB 2.0 full-speed dual port Device/Host/OTG Controller with

on-chip PHY and associated DMA controller.

▬Four UARTs with fractional baud rate generation one with

modem control I/O one with IrDA support all with FIFO.

▬CAN controller with two channels.

▬SPI controller.

▬Two SSP controllers with FIFO and multi-protocol capabilities.

One is an alternate for the SPI port sharing its interrupt. SSPs

can be used with the GPDMA controller.

▬Three I2C-bus interfaces (one with open-drain and two with

standard port pins).

▬I2S (Inter-IC Sound) interface for digital audio input or output.

It can be used with the GPDMA.

● Other peripherals:

▬SD/MMC memory card interface.

▬160 General purpose I/O pins with configurable pull-up/down

resistors.

▬10-bit ADC with input multiplexing among 8 pins.

▬10-bit DAC.

▬Four general purpose timers/counters with 8 capture inputs

and 10 compare outputs. Each timer block has an external

count input.

▬Two PWM/timer blocks with support for three-phase motor

control. Each PWM has an external count inputs.

▬RTC with separate power domain clock source can be the RTC

oscillator or the APB clock.

▬2 kB SRAM powered from the RTC power pin allowing data to

be stored when the rest of the chip is powered off.

▬WatchDog Timer (WDT). The WDT can be clocked from the

internal RC oscillator the RTC oscillator or the APB clock.

● Standard ARM test/debug interface for compatibility with existing

tools.

● Emulation trace module supports real-time trace.

● Single 3.3 V power supply (3.0 V to 3.6 V).

● Three reduced power modes: idle sleep and power-down.

● Four external interrupt inputs configurable as edge/level sensitive.

All pins on PORT0 and PORT2 can be used as edge sensitive

interrupt sources.

● Processor wake-up from Power-down mode via any interrupt able to

operate during Power-down mode (includes external interrupts RTC

interrupt USB activity Ethernet wake-up interrupt CAN bus

activity PORT0/2 pin interrupt).

● Two independent power domains allow fine tuning of power

consumption based on needed features.

● Each peripheral has its own clock divider for further power saving.

These dividers help reducing active power by 20 - 30 %.

● Brownout detect with separate thresholds for interrupt and forced

reset.

● On-chip power-on reset.

On-chip crystal oscillator with an operating range of 1 MHz to 24 MHz.

● 4 MHz internal RC oscillator trimmed to 1 % accuracy that can

optionally be used as the system clock. When used as the CPU clock

does not allow CAN and USB to run.

● On-chip PLL allows CPU operation up to the maximum CPU rate

without the need for a high frequency crystal. May be run from the

main oscillator the internal RC oscillator or the RTC oscillator.

● Boundary scan for simplified board testing.

● Versatile pin function selections allow more possibilities for using

on-chip peripheral functions.

BLOCK DIAGRAM:

MEMORY MAP:

LPC2468 memory map

SCHEMATIC:

BOARD LAYOUT:

POWER SUPPLY CIRCUIT:

LPC-E2468 can take power from power connector PWR where +(9-12) VDC

or (6-9) VAC external voltage source has to be applied. The board could also

take power from USB_D or from battery. Note: the battery only supplies the

internal 2MB SRAM and the RTC.

The board power consumption is: about 150 mA at 9VDC.

RESET CIRCUIT:

LPC-E2468 reset circuit is made with RC group R4 – 47K C20 – 100nF

and RESET button.

CLOCK CIRCUIT:

Quartz crystal 12MHz is connected to LPC2468 pin 44 (XTAL1) and pin 46

(XTAL2).

32.768 KHz quartz crystal is connected to LPC2468 pin 34 (RTCX1) and

pin 36 (RTCX2) for its internal Real Time Clock.

JUMPER DESCRIPTION:

3 3V_E

This jumper when closed supplies 3.3 V voltage to the

VDD1-10 pins of the MCU.

Default state is closed.

3 3VA_E

This jumper when closed supplies 3.3 V voltage to the VDDA

pin of the MCU.

Default state is closed.

VREF_E

This jumper when closed supplies 3.3 V reference voltage to

the VREF pin of the MCU.

Default state is closed.

PHY_PD

This jumper controls the PHY signal of the Ethernet controller.

If the jumper is pen the PHY is always enabled if the pin is closed the MCU

controls the PHY.

Default state is open .

WP_E

This jumper when closed inputs the Write protect signal from

the SD/MMC card to the MCU.

Default state is closed .

NF_WPE

This jumper when closed write-protects the flash and when

open disables the write protection.

Default state is open .

N_CE/CS1

When 1-2 is shorted, you could select the flash memory for

work throu h the Chip Select 1 si nal. If 2-3 is shorted, the #CE

pin of the NAND flash memory is connected to the N_CE pin of the

MCU.

Default position is 1-2 shorted.

ISP_E

If you put this jumper you enable the ISP (In-System

Programming). This is used when you want external software to program the

LCP2478 This jumper is used in combination with the RST_E jumper.

Default state is open.

RST_E

If you put this jumper you enable external software to control

the Reset signal to the processor. This is used when you want external

software to program the LCP2478 This jumper is used in combination with the ISP_E

jumper.

Default state is open.

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