North Atlantic 75DS2 Manual de usuario

75DS2 Operations Manual

North Atlantic Industries, Inc.

11/11/2011

Rev: 2011-11-11-1000

www.naii.com

Page 1 of 43

75DS2

3U cPCI SYNCHRO/RESOLVER or

LVDT/RVDT CONVERTER

OPERATIONS MANUAL

75DS2 Operations Manual

North Atlantic Industries, Inc.

11/11/2011

Rev: 2011-11-11-1000

www.naii.com

Page 2 of 43

MODEL 75DS2

3U cPCI SYNCHRO/RESOLVER or LVDT/RVDT

CONVERTER

Convection Cooled

Features

1, 2, 3, or 4 Synchro/Resolver (D/S) or

LVDT/RVDT (DLV) simulation channels

1 arc-minute (0.0167°) accuracy

16 bit resolution

1.5, 2.2 or 3 VA drive capability per

synchro channel

Automatic background BIT testing

continually checks and reports the health

of each channel

Optional onboard 3 VA programmable

reference supply

Connections via front panel, rear

connector or both

Convection and conduction-cooled

Wrap-around converters for reading actual

commanded outputs

No adjustments or trimming required

Wide operating temperature range

Software support kit and drivers are

available

Conduction Cooled

Description

The 75DS2 is a 3U cPCI board which incorporates up to 4 Digital-to-Synchro/Resolver converters with

1.5, 2.2 or 3 VA drive capability; or 2 or 4 isolated DLV converters. The board features continuous

background BIT testing, reference and signal loss detection. Each channel is independent, isolated

and enables the user to ground one of the outputs without affecting performance. This model drives

passive or active loads. In addition, the card provides an optional onboard reference supply.

Automatic background BIT testing, an important feature, is always enabled and continually checks the

health of each channel. There is no need to guess or make assumptions about system performance. A

fault is immediately reported and the specific channel is identified. This diagnostic capability is of

tremendous benefit because it immediately identifies and reports a failure, without the need to shut

down the equipment for troubleshooting. Testing is totally transparent to the user, requires no external

programming, and has no effect on the standard operation of the card.

75DS2 Operations Manual

North Atlantic Industries, Inc.

11/11/2011

Rev: 2011-11-11-1000

www.naii.com

Page 3 of 43

Table of Contents

MODEL 75DS2...........................................................................................................................................................2

3U CPCI SYNCHRO/RESOLVER OR LVDT/RVDT CONVERTER..........................................................................2

FEATURES ................................................................................................................................................................2

DESCRIPTION ...........................................................................................................................................................2

SPECIFICATIONS......................................................................................................................................................6

General –for the Mother Board...............................................................................................................................................6

D/S (Module 3*, 4*) –One Isolated Digital-to-SYN/RSL Ch, 3.0 VA Output............................................................................6

D/S (Module 1*,2*) –Two Isolated Digital-to-SYN/RSL Ch, 1.5/2.2 VA Outputs.....................................................................6

DLV (Module 5*) –Two/Four Isolated DLV Simulation Ch, LVDT/RVDT Outputs...................................................................7

Reference (Module W6, W7)–Optional, Isolated, On-Board Reference Supply .....................................................................8

Product Configuration and Memory Map.................................................................................................................................9

MEMORY MAP........................................................................................................................................................................9

D/S ONE/TWO CHANNEL (MODULES 1*, 2*, 3*, 4*)............................................................................................ 10

Principle of Operation............................................................................................................................................................10

Built-In Test (BIT) / Diagnostic Capability..............................................................................................................................10

Wrap S/D Angle (Read).........................................................................................................................................................11

Measured Reference Voltage................................................................................................................................................11

Measured Signal Voltage ......................................................................................................................................................11

Signal Loss Threshold...........................................................................................................................................................11

Reference Loss Threshold ....................................................................................................................................................11

D/S Channel Frequency........................................................................................................................................................11

D/S Status, Signal Loss.........................................................................................................................................................12

D/S Wrap Select, Internal/External (Pending) .......................................................................................................................12

D/S Status, External Amplifier (Pending)...............................................................................................................................12

D/S Write Angle –Single Speed............................................................................................................................................12

D/S Write Angle –Two Speed...............................................................................................................................................12

D/S Rotation..........................................................................................................................................................................13

D/S Stop Angle......................................................................................................................................................................13

D/S Set Rotation Rate...........................................................................................................................................................13

D/S Rotation Mode, Continuous or Start/Stop.......................................................................................................................13

D/S Rotation Status...............................................................................................................................................................13

Start Rotation ........................................................................................................................................................................13

Stop Rotation.........................................................................................................................................................................13

D/S Set Reference Voltage ...................................................................................................................................................14

D/S Set Signal Voltage..........................................................................................................................................................14

D/S BIT Test Enable..............................................................................................................................................................14

D/S Status, BIT Test..............................................................................................................................................................15

Test (D2) Verify .....................................................................................................................................................................15

D/S Ratio 1/2.........................................................................................................................................................................15

D/S Output Mode...................................................................................................................................................................15

D/S Synchro / Resolver Select ..............................................................................................................................................16

D/S Torque Receiver Select..................................................................................................................................................16

D/S Trigger Source Select.....................................................................................................................................................16

D/S Trigger Slope Select.......................................................................................................................................................16

D/S Module Power Enable ....................................................................................................................................................16

D/S Output Enable.................................................................................................................................................................16

D/S Active Channel Select ....................................................................................................................................................17

D/S Status, Reference Loss..................................................................................................................................................17

D/S Status, Phase Lock Loss................................................................................................................................................17

D/S Set Phase Offset ............................................................................................................................................................17

Reference Loss Interrupt Enable...........................................................................................................................................17

Signal Loss Interrupt Enable .................................................................................................................................................18

BIT Test Fail Interrupt Enable................................................................................................................................................18

Phase Lock Loss Interrupt Enable.........................................................................................................................................18

OSC (Optional Onboard Reference Supply) Set Frequency .................................................................................................18

OSC (Optional Onboard Reference Supply) Set Voltage......................................................................................................19

Interrupt Vector......................................................................................................................................................................19

D/S (1*, 2*, 3*, 4*) (PCI) MODULE MEMORY MAP............................................................................................... 20

DLV TWO/FOUR CHANNEL (MODULE 5*)........................................................................................................... 21

Principle of Operation............................................................................................................................................................21

75DS2 Operations Manual

North Atlantic Industries, Inc.

11/11/2011

Rev: 2011-11-11-1000

www.naii.com

Page 4 of 43

Built-in Test/Diagnostic Capability.........................................................................................................................................21

Wrap LVDT Position (Read)..................................................................................................................................................21

Wrap (LVDT) Velocity............................................................................................................................................................22

DLV Channel Signal Voltage.................................................................................................................................................22

DLV Channel Excitation Voltage............................................................................................................................................22

Signal Loss Threshold...........................................................................................................................................................22

Excitation Loss Threshold .....................................................................................................................................................22

DLV Write Position ................................................................................................................................................................22

DLV Response / Filter Time ..................................................................................................................................................22

Status, Signal Loss................................................................................................................................................................23

DLV Channel Frequency.......................................................................................................................................................23

DLV Set Channel Excitation Voltage.....................................................................................................................................23

DLV Set Channel Signal Voltage...........................................................................................................................................23

DLV BIT Test Enable.............................................................................................................................................................24

Test (D2) Verify .....................................................................................................................................................................24

DLV Output Mode..................................................................................................................................................................24

DLV 2-Wire or 3/4-Wire Select..............................................................................................................................................24

DLV Module Power Enable ...................................................................................................................................................25

DLV Current ..........................................................................................................................................................................25

DLV Active Channel Select ...................................................................................................................................................25

DLV Status, Excitation Loss..................................................................................................................................................25

DLV Status, Phase Lock Loss...............................................................................................................................................25

DLV Set Phase Offset ...........................................................................................................................................................25

DLV Current Threshold..........................................................................................................................................................25

OSC (Onboard) Excitation Set Frequency.............................................................................................................................26

OSC (Onboard) Excitation Set Voltage .................................................................................................................................26

DLV Status, BIT Test.............................................................................................................................................................27

Excitation Loss Interrupt Enable............................................................................................................................................27

Signal Loss Interrupt Enable .................................................................................................................................................27

BIT Test Fail Interrupt Enable................................................................................................................................................27

Phase Lock Loss Interrupt Enable.........................................................................................................................................27

Interrupt Vector......................................................................................................................................................................28

2/4 CH DLV (5*) (PCI) MODULE MEMORY MAP.................................................................................................. 29

OPTIONAL ONBOARD REFERENCE CONTROL ................................................................................................ 30

OSC (Optional Onboard Reference Supply) Set Frequency .................................................................................................30

OSC (Optional Onboard Reference Supply) Set Voltage......................................................................................................30

PCI Memory Map...................................................................................................................................................................30

GENERAL USE REGISTER MEMORY MAP......................................................................................................... 31

MEMORY MAP......................................................................................................................................................................31

Part Number..........................................................................................................................................................................31

Serial Number........................................................................................................................................................................31

Date Code.............................................................................................................................................................................31

Revisions...............................................................................................................................................................................31

Board Ready .........................................................................................................................................................................31

Watchdog Timer....................................................................................................................................................................31

Soft Reset..............................................................................................................................................................................31

Design Version......................................................................................................................................................................31

Platform.................................................................................................................................................................................32

Model.....................................................................................................................................................................................32

Generation.............................................................................................................................................................................32

Special Spec .........................................................................................................................................................................32

Interrupt Flow for PCI/cPCI....................................................................................................................................................33

75DS2 CONNECTOR/PIN-OUT INFORMATION................................................................................................... 34

Front Panel Connectors J3, J4:.............................................................................................................................................34

Rear Panel Connectors J1, J2:..............................................................................................................................................34

Optional Onboard Reference Output.....................................................................................................................................34

NAI Synchro / Resolver Naming Convention.........................................................................................................................35

SLOT 1 D/S OR DLV.............................................................................................................................................................35

SLOT 2 D/S OR DLV.............................................................................................................................................................36

Dimensions............................................................................................................................................................................37

PART NUMBER DESIGNATION............................................................................................................................ 38

Two Channel D/S Module Code Table..................................................................................................................................40

75DS2 Operations Manual

North Atlantic Industries, Inc.

11/11/2011

Rev: 2011-11-11-1000

www.naii.com

Page 5 of 43

Single Channel D/S Module Code Table...............................................................................................................................41

2/4 Channel DLV Module Code Table...................................................................................................................................42

REVISION PAGE .................................................................................................................................................... 43

Specifications

75DS2 Operations Manual

North Atlantic Industries, Inc.

11/11/2011

Rev: 2011-11-11-1000

www.naii.com

Page 6 of 43

SPECIFICATIONS

General –for the Mother Board

Signal Logic Level:

Automatically supports either 5V or 3.3V CPCI bus

Power (Motherboard):

+5 VDC @ 750mA and ±12V @ 15mA, then add pwer for each individual

module

Temperature, Operating:

“C” =0°C to +70°C; “E”=-40°C to +85°C (See part number)

Storage Temperature:

-55°C to +105°C

Size:

Height -3.94” / 100 mm (3U)

Width -0.8” / 20.3 mm (4HP)

Depth –6.3” / 160 mm

Weight:

4 oz. (115 g) unpopulated,

Add weight for each module (typically 1 oz. each)

Add 2oz. (57g) for reference supply

Add 2 oz. (57g) for wedgelocks

D/S (Module 3*, 4*) –One Isolated Digital-to-SYN/RSL Ch, 3.0 VA Output

*See P/N

(Applies to each channel unless noted otherwise)

Resolution:

16 bits (.0055°)

Accuracy:

0.067º (4 arc minutes) for passive loads; 30 arc minutes for TR’s

Output Format:

Synchro or Resolver, (see part number), galvanic isolation

Output Voltage:

(See code table and part number)

Output Load:

3.0 VA max. /Channel. Short circuit protected

Output Control:

Channel output can be turned ON/OFF

Regulation (VL-L):

5% max. No load to Full load

Rotation:

Continuous rotation or programmable Start and Stop angles. 0 to 13.6 RPS with a

resolution of 0.15/sec. Step size is 16 bits (0.0055)° up to 1.5 RPS, then linearly

increases to 12 bits (0.088°) at 13.6 RPS

Reference Input Voltage:

2 to 115Vrms, Galvanic isolated. Uses @ 1 ma max/Channel

Reference Frequency:

47 Hz to 10 KHz (See part number)

Phase Shift:

0.5° max. (Between output and reference)

Programmable Phase Shift:

Programmable, ± 90with 0.1resolution

Settling Time:

Less than 100 microseconds

Module Power:

+5VDC @ 50 mA

±12VDC @ 115 mA (no-load); (Add 1.1 watts of ±12V for every VA of output).

Therefore, a 3.0 VA Load adds to ±12VDC 138 mA average, or 157 mA peak

External ±12VDC input power can be utilized

Ground:

Isolated signal and reference. Channels individually isolated from each other and

from system ground

Weight:

1.5 oz. (42g)

D/S (Module 1*,2*) –Two Isolated Digital-to-SYN/RSL Ch, 1.5/2.2 VA Outputs

*See P/N

(Applies to each channel unless noted otherwise)

Resolution:

16 bits (.0055°)

Accuracy:

±1 arc-minute (.017°) from No Load to Full Load

Output Format:

Synchro or Resolver (see part number), galvanic isolation

Output Voltage:

(See code table and part number)

Output Load:

1.5 VA @ 11.8 VLL or 28 VLL, and 2.2 VA @ 90 VLL max. per Channel

(Power reduces linearly as output voltage is reduced.) Shortcut circuit protected

Output Control:

Module outputs can be turned ON/OFF

Regulation (VL-L):

5% max. No load to Full load

Specifications

75DS2 Operations Manual

North Atlantic Industries, Inc.

11/11/2011

Rev: 2011-11-11-1000

www.naii.com

Page 7 of 43

Ratio:

Dual speed, Programmable, Set any ratio between 2 and 255

Rotation:

Continuous rotation or programmable Start and Stop angles. 0 to 13.6 RPS with

a resolution of 0.015/sec. Step size is 16 bits (0.0055)° up to 1.5 RPS, then

linearly increases to 12 bits (0.088°) at 13.6 RPS

Reference Input Voltage:

2 to 115Vrms, Galvanic isolation. Uses 1 ma max/Channel

Reference Frequency:

47 Hz to 10 KHz (See part number)

Phase Shift:

0.5° max. (between output and reference)

Programmable Phase Shift:

Programmable, ± 90with 0.1resolution

Settling Time:

Less than 100 microseconds

Module Power:

+5VDC @ 570 mA ±12VDC @ 160 mA (no-load) per channel

(Add 2.9 watts of ±12VDC for every VA of output per channel)

Therefore, a 1.5 VA Load adds to ±12V 181 mA average, or 288 mA peak per channel

External ±12V input power can be utilized

Ground:

Isolated signal and reference. Channels individually isolated from each other and

from system ground

Weight:

1.5 oz. (42 g)

DLV (Module 5*) –Two/Four Isolated DLV Simulation Ch, LVDT/RVDT Outputs

*See P/N

(Applies to each channel unless noted otherwise)

Number of Channels:

2 (3/4-wire) / 4 (2-wire)

Resolution:

16 bits (.001526% FS)

Linearity:

0.1% FS

Output Gain:

0.1%

Output Format:

Configurable for either 3/4-wire or 2-wire.Galvanically isolated. Output voltage

is programmable fixed or ratio-metric

Output Voltage:

Programmable (See code table and part number)

Output Load:

1.5 VA max @ 11.8 VRMS or 28 VRMS (de-rates linearly as voltage is

decreased) (See code table)

Regulation (VL-L):

5% max. No load to Full load

Excitation Input Voltage:

(See part number), Galvanic isolated. Uses 1 ma max/Channel

Excitation Frequency:

47 Hz to 10 kHz (See part number)

Phase Shift (A/B):

0.5° max. (Between output and reference) (Programmable phase shift)

Settling Time:

Less than 100 microseconds

Module Power:

+5VDC @ 570 mA

±12VDC @ 160 mA (no-load) per channel. (Add 2.9 watts of ±12VDC for every

VA of output per channel). Therefore, a 1.5 VA Load adds to ±12V 181 mA

average, or 288 mA peak per channel

External ±12V input power can be utilized

Ground:

Isolated signal and excitation; Channels individually isolated from each other

and from system ground

Weight:

1.5 oz. (42g)

Specifications

75DS2 Operations Manual

North Atlantic Industries, Inc.

11/11/2011

Rev: 2011-11-11-1000

www.naii.com

Page 8 of 43

Voltage (V) Output (Programmed)

Power Output (VA)

2.0

4.0

6.0

Max Current ~ 420 mA

Power Derating Curves:

Voltage Range (Vrms) Max Current (mA) Power Derating

2 - 11.9 420 5 VA @ 11.8 Vrms

(Power derates linearly to 0.84 VA @ 2.0 Vrms)

12 -27.9 420 to 192 5 VA @ 26.0 Vrms (Power constant to 12.0 Vrms)

115 43 5 VA @ 115 Vrms (fixed)

2 - 10 V Frequency Range: 47 –15000 Hz

(5 VA max @ 15 KHz then reduces linearly to 1.5 VA @ 20 KHz 10.1 –28 V Frequency Range: 47 –10000 Hz

5VA Power Constant

Max Current ~ 420mA to 192 mA

(w/ voltage inversely proportional)

0.5

1.4

Reference (Module W6, W7)–Optional, Isolated, On-Board Reference Supply

Voltage Output:

Note: Identify voltage output option in P/N option selection

(Improved version to 5 VA introduced DOM 6/11)

Vrms to 28 Vrms, Programmable with a resolution of 0.1 V

2.0 to 10.0 Vrms / 47 Hz to 20 KHz frequency range

10.1 to 28.0 Vrms / 47 Hz to 10 KHz frequency range

115 Vrms fixed

115.0 Vrms / 47 Hz to 2.0 KHz frequency range

Accuracy (No Load):

2% of setting ≤ 10 KHz

5% of setting > 10 KHz

Regulation:

10% (No Load to Full Load)

Output Drive:

5 VA maximum ≤ 15 KHz

5 VA –1.5 VA (decreased linearly from 15 KHz to 20 KHz)

(See detailed description of Output Drive)

Output Protection:

Over-current (10x automatic retry; @ 1.3 sec int.; afterwards, shutdown w/ manual

reset)

Frequency:

47 Hz to 20 KHz Programmable with 0.1 Hz steps

Frequency Accuracy:

0.1% of programmed frequency or 1 Hz (whichever is greater)

THD:

2% (maximum)

Reference Output Drive:

(See detailed characterization)

Power:

+5 VDC @ 10 mA

±12 VDC @ 120 mA (Quiescent, no load, max)

Add ±12 VDC @ 40 mA for every 1 VA Load

Ground:

Output isolated from system ground

Weight:

1 oz. (28g)

Specifications

75DS2 Operations Manual

North Atlantic Industries, Inc.

11/11/2011

Rev: 2011-11-11-1000

www.naii.com

Page 9 of 43

Product Configuration and Memory Map

This design provides multiple functions on a single cPCI (3U) card. When ordering, the customer selects an

assortment of up to 2 modules to populate this 2-slot “motherboard.” The memory map follows the order of

modules specified in the part number.

To address the register of any module, use the Base address to the entire card, add the Module Offset

depending upon its slot (000 or 800), and then add the Register Offset of interest (see module memory map.)

The memory map of each selected module counts from, or is superimposed over its respective module offset.

Thus, Address = Base + Module Offset + Register Offset.

For example, if a Digital I/O module were selected to populate module 1 and a Discrete I/O module were

selected to populate module 2:

Address = Base + Module 1 Offset 000 + Digital I/O register 010 = Base + 010 hex

Address = Base + Module 2 Offset 800 + Discrete I/O register 024 = Base + 824 hex

MEMORY MAP

000

Module 1 Register…

800

Module 2 Register…

3000

Unit Level General Register…

004

804

3004

008

808

3008

00C

80C

300C

010

810

3010

7FE

FFE

37FE

7FF

FFF

37FF

Any address NOT SPECIFIED within 4096 byte block (up to 3FFFh) is reserved.

The memory map of each module type is described hereafter:

Slot 2

Offset 800

Slot 1

Offset 000

General

Offset 3000

D/S One/Two Channel (Modules 1*, 2*, 3*, 4*)

75DS2 Operations Manual

North Atlantic Industries, Inc.

11/11/2011

Rev: 2011-11-11-1000

www.naii.com

Page 10 of 43

Wrap-Around

Test

S/D

DS 1

DS 2

State

Machine

DS Module Block Diagram

Module Bus

User Interface

Wrap-Around

Test

S/D

Signal and Reference

Isolation

D/S ONE/TWO CHANNEL (MODULES 1*, 2*, 3*, 4*)

(*See part number designation)

Principle of Operation

These new Digital-to-Synchro/Resolver (D/S)

modules are solid state designs that eliminate

the need for external transformers. Since these

modules operate down to 50 Hz, deleting the

previously large external transformers offers

huge space savings. The reduced size and

lower power consumption of these modules now

makes it possible to supply 10 channels on a 6U

card.

Two different modules are available within the

same package size: The first is a two-channel

1.5VA/2.2VA design that contains two separate

channels within one enclosure. The other is a

single channel 3.0VA design that will also drive

Torque Receivers. All outputs are short circuit

protected and the S2 (Z) leg can be grounded

without effecting performance. Any channel can be programmed for rotation (either continuous or with start/stop

angles). External amplifiers can be added to drive up to 30 VA with a frequency range of 50 to 400 Hz. Two-

speed (up to 1:255 ratio) outputs can be programmed (dual channel module). The processor will set a flag when it

senses that the maximum allowable misalignment of 90/gear ratio is exceeded.

New features in these modules now include a wrap capability for measuring each channel’s commanded output

angle and carrier frequency. The module’s extensive programmability now includes format selection (synchro or

resolver). A background calibration feature (pending), that is totally transparent to the operation of the channels,

constantly adjusts outputs for all load and environmental conditions. Each channel can be programmed for a

different output voltage, which can be programmed for either ratio-metric or absolute (fixed) output. Module power

ON/OFF capability provided for shutting down inactive channels.

Built-In Test (BIT) / Diagnostic Capability

Two different tests (one on-line and one off-line) can be selected:

The on-line (D2) Test initiates automatic background BIT testing that checks the output accuracy of each

channel by comparing the measured output angle to the commanded angle. Each channel is individually checked

to an accuracy of 0.2and each D/S Signal output and Reference input is continually monitored. User can

periodically clear to 00h and then read Test (D2) verification register again, after 0.1 seconds, to verify that

background bit testing is activated. Any failure triggers an Interrupt (if enabled) and the results are available in

Status Registers. The testing is totally transparent to the user, requires no external programming, has no effect on

the standard operation of the card, and can be enabled or disabled.

The off-line (D3) Test initiates a BIT test that generates and tests 24 different angles to a test accuracy of 0.2.

Results can be read from registers. External reference is required and outputs must be on. Any failure triggers an

Interrupt (if enabled). Testing requires no external programming, and can be initiated or stopped at any time.

CAUTION: Outputs must be ON and Reference supplied during this test and therefore active. Check

connected loads for possible interaction.

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