Quick Start Guide: LPC435x-Xplorer++
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2.5 LPC435x description
The LPC435x is ARM Cortex-M4 based microcontroller for embedded applications which include an
ARM Cortex-M0 coprocessor, up to 1 MB of flash and 136 kB of on-chip SRAM, 16 kB of EEPROM
memory, a quad SPI Flash Interface (SPIFI), advanced configurable peripherals such as the State
Configurable Timer (SCT) and the Serial General Purpose I/O (SGPIO) interface, two High-speed USB
controllers, Ethernet, LCD, an external memory controller, and multiple digital and analog peripherals.
The LPC435x operate at CPU frequencies of up to 204 MHz.
Cortex-M4 Processor core
ARM Cortex-M4 processor, running at frequencies of up to 204 MHz.
ARM Cortex-M4 built-in Memory Protection Unit (MPU) supporting eight regions.
ARM Cortex-M4 built-in Nested Vectored Interrupt Controller (NVIC).
Hardware floating-point unit.
Non-maskable Interrupt (NMI) input.
JTAG and Serial Wire Debug (SWD), serial trace, eight breakpoints, and four watch points.
Enhanced Trace Module (ETM) and Enhanced Trace Buffer (ETB) support.
System tick timer.
Cortex-M0 Processor core
ARM Cortex-M0 co-processor capable of off-loading the main ARM Cortex-M4 application
processor.
Running at frequencies of up to 204 MHz.
JTAG
Built-in NVIC.
On-chip memory
Up to 1 MB on-chip dual bank flash memory with flash accelerator.
16 kB on-chip EEPROM data memory.
136 kB SRAM for code and data use.
Multiple SRAM blocks with separate bus access. Two SRAM blocks can be powered down
individually.
64 kB ROM containing boot code and on-chip software drivers.
64 bit of general-purpose One-Time Programmable (OTP) memory.
Configurable digital peripherals
Serial GPIO (SGPIO) interface.
State Configurable Timer (SCT) subsystem on AHB.
Global Input Multiplexer Array (GIMA) allows to cross-connect multiple inputs and outputs to
event driven peripherals like the timers, SCT, and ADC0/1.
Serial interfaces
Quad SPI Flash Interface (SPIFI) with four lanes and up to 52 MB per second.
10/100T Ethernet MAC with RMII and MII interfaces and DMA support for high throughput at
low CPU load. Support for IEEE 1588 time stamping/advanced time stamping (IEEE 1588-2008
v2).
One High-speed USB 2.0 Host/Device/OTG interface with DMA support and on-chip high-
speed PHY. One High-speed USB 2.0 Host/Device interface with DMA support, on-chip full-
speed PHY and ULPI interface to external high-speed PHY.
USB interface electrical test software included in ROM USB stack.
One 550 UART with DMA support and full modem interface.
Three 550 USARTs with DMA and synchronous mode support and a smart card interface
conforming to ISO7816 specification. One USART with IrDA interface.
