Linear Technology DC1485A Guía de configuración rápida

dc1485af

DEMO MANUAL DC1485A

DESCRIPTION

LTC2757:

18-Bit, Parallel Input,

SoftSpan IOUT DAC

Demonstrationcircuit1485AfeaturestheLTC

2757A single

18-bitSoftSpan™IOUT DAC with ±1LSBmaximumINL.This

device features six programmable output ranges: 0V to 5V,

0V to 10V, ± 5V, ±10V, ±2.5V and –2.5V to 7.5V. The demo

circuit allows all of the LTC2757’s features to be exercised,

including system-level gain and offset adjustments.

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and

SoftSpan is a trademark of Linear Technology Corporation. All other trademarks are the property

of their respective owners.

Design ﬁles for this circuit board are available at

http://www.linear.com/demo

DAC

CONNECTIONS

ANALOG POWER SUPPLY

(NORMALLY ±15V)

RIBBON CABLE

TO DC590

CONTROLLER

Figure 1. Connection Diagram

dc1485af

DEMO MANUAL DC1485A

QUICK START PROCEDURE

Connect a clean ±15V power supply to the turret posts at

the bottom of the DC1485A board. Connect J1 to a DC590

USB serial controller using the supplied 14-conductor rib-

bon cable. Connect DC590 to a host PC with a standard

USB A/B cable. Run the evaluation software supplied with

DC590 or download it from www.linear.com/software. The

correct control panel will be loaded automatically. The

software automatically setsthe LTC2757 outputs according

to the entries in the control panel. A square wave option is

available to test settling time. MSPAN jumper should be in

the lower position if software span control is desired.

Additional software documentation may be available

from the Help menu item, as features may be added

periodically.

dc1485af

DEMO MANUAL DC1485A

USING THE PARALLEL CONNECTOR

Protocol

The DC1485A can be used without the DC590 system. If

a DC590 demo board is not connected the shift registers

on the DC1485A are disabled, allowing the user to clock

in data through the parallel connector (P1).

The data input register is loaded directly from the 18-bit

microprocessor bus (D0-D17 on the parallel connector)

by holding the _D/S pin low and then pulsing the _WR

pin low. The second register (DAC register) is loaded by

pulsing the UPD pin high, which copies the data held in

the input register into the DAC register. Note that updates

always include both data and span; but the DAC register

values will not change unless the input register values

have been changed by writing.

Loadingthe span inputregister is accomplishedin a similar

manner, by holding the _D/S pin high and then bringing

the _WR pin low. The span and data register structures

are the same except for the number of parallel bits. The

span registers have three bits, while the data registers

have 18 bits.

Please see the LTC2757 data sheet for in depth timing

diagrams and more information about the communica-

tion protocol.

Parallel Pin Descriptions

D0-D17: DAC Input/Output Data Bits. These I/O pins set

and read back the DAC code. D17 is the MSB. D0 is the

LSB.

S0-S2: Span Input/Output. Pins S0, S1 and S2 are used to

program and to read back the output range of the DAC.

_D/S: Data/Span Select: This pin is used to select acti-

vation of the data or span I/O pins (D0 to D17 or S0 to

S2, respectively), along with their respective dedicated

registers, for write or read operations. Update operations

ignore _D/S, since all updates affect both data and span

registers. For single-span operation, tie _D/S to GND.

READ: Read Pin. When READ is asserted high, the data

I/O pins (D0-D17) or span I/O pins (S0-S2) output the

contentsof the selected register. For single-span operation,

readback of the span I/O pins is disabled.

UPD: Update and Buffer Select Pin. When READ is held low

and UPD is assertedhigh,the contentsof theinput registers

(both data and span) are copied into their respective DAC

registers. The output of the DAC is updated, reﬂecting the

new DAC register values. When READ is held high, the

update function is disabled and the UPD pin functions as

a buffer selector—logic low to select the input register,

high for the DAC register.

_WR: Active Low Write Pin. A Write operation copies

the data present on the data or span I/O pins (D0-D17 or

S0-S2, respectively) into the input register. When READ

is high, the Write function is disabled.

MSPAN: Manual Span Control Pin. MSPAN is used to

conﬁgure the LTC2757 for operation in a single, ﬁxed

output range.

G: Ground Pin. (Note, if an IDE cable is used, Pin 21 is

often keyed on the connector and may be trimmed.)

dc1485af

DEMO MANUAL DC1485A

HARDWARE SETUP

Jumpers

MSPAN: Manual Span Control Pin. MSPAN is used to

conﬁgure the LTC2757 for operation in a single, ﬁxed

output range. If MSPAN is high it will be conﬁgured for

single-span use. If MSPAN is low it will be set through the

Quick Eval Software. Default position is 0 (low).

S0, S1, S2: Used to set the ﬁxed output range if MSPAN

is high. Default position is 0, 0, 0 (0V to 5V).

S2 S1 S0 SPAN

0 0 0 0V to 5V

0 0 1 0V to 10V

010±5V

0 1 1 ±10V

1 0 0 ±2.5 V

1 0 1 –2.5V to 7.5V

REFADJ: Gain Adjust Pin. If no adjustments are required,

select GND. Selecting Ext connects the pin to the turret

allowing external adjustment to null gain error or com-

pensate for reference errors.

RVOS: Offset adjustment selection for DACA. If no offset

adjustment is required,select GND.SelectingEXT connects

the offset pin to the turret allowing external adjustment

of offset.

VCC:Select source for 5V VCC supply. Set to 5V for supply

by onboard LT1236 reference (recommended). Set to REG

to be supplied by regulated supply from DC590 Controller

and remove the jumper to supply externally.

Analog Connections (Turret Posts)

VOUT: DAC Voltage Output.

VREF:DAC Reference Voltage. If the onboard LT1236 refer-

ences are selected, the voltage may be measured at these

points. If a remote reference is selected, then an external

reference must be applied to these points.

VOSA: DAC Offset Adjust Input. Use only if VOSA jumper

set to EXT. Nominal input range is ±5V.

REFADJ: Gain Adjust Pin. This voltage-control pin can be

used to null gain error or to compensate for reference er-

rors. The gain error change expressed in LSB is the same

for any output range.

Power and Ground Connections

Analog Power: The 15V, –15V and GND turret posts are

the analog supplies for the internal DAC ampliﬁers. These

should be connected to a well regulated, low noise power

supply.

VCC:Connection to VCC. See schematic and description

for VCC jumper.

Grounding: Separate power and signal grounds are pro-

vided. Signal GND is the turret closest to VOUT

, use this

for measurement ground and output return. Power GND

is between AMP V+and AMP V–turrets.

dc1485af

DEMO MANUAL DC1485A

PARTS LIST

ITEM QTY REFERENCE PART DESCRIPTION MANUFACTURE/PART NUMBER KIT QTY

NUMBER OF BOARDS = 175

1 16 C1-C4, C6-C8, C10-C12, C19, C25,

C29, C31, C33, C40

CAP., X5R, 0.1μF 25V 20%, 0402 TDK, C1005X5R1E104M 2800

2 2 C5, C20 CAP., NP0, 100pF 50V, 5%,1206 AVX, 12065A101JAT2A 350

3 1 C9 CAP., X7R, 1μF 25V 10%, 0805 TDK, C2012X7R1E105K 175

4 2 C34, C37 CAP., X5R, 1μF 25V 20%, 0603 TDK, C1608X5R1E105M 350

5 6 C13, C18, C30, C36, C39, C41 CAP., X5R, 10μF 25V 20%,1206 TDK, C3216X5R1E106M 1050

6 1 C14 CAP., X7R, 1μF 25V 10%,1206 AVX, 12063C105KAT2A 175

7 0 C15, C16 CAP., 0603 OPT 0

8 0 C21 CAP., 1206 OPT 0

9 3 C17, C23, C28 CAP., NP0, 100pF 50V, 5%,0402 AVX, 04025A101JAT2A 525

10 2 C38, C35 CAP., X7R, 0.01μF 25V 20%,0402 TDK, C1005X7R1E103M 350

11 3 D1, D2, D5 DIODE, SCHOTTKY, SOT23 DIODES INC., BAT54C-7-F 525

12 9 E1, E2, E3, E4, E5, E6, E7, E8, E9 TEST POINT, TURRET, 0.064" MILL-MAX, 2308-2-00-80-00-00-07-0 1575

13 3 JP1, JP2, JP3 JMP, 2X3, 0.079" SAMTEC, TMM-103-02-L-D 525

14 2 JP4, JP5 JMP, 1X3, 0.079" SAMTEC, TMM-103-02-L-S 350

15 1 J1 HEADER, 2X7 PIN, 0.079CC MOLEX, 87831-1420 175

16 0 J2 CONN, BNC, RTANG 50Ω OPT (TYCO ELEC. AMP, 413631-1) 0

17 1 P1 JMP, 2X20, 0.100" SAMTEC, TSW-120-07-L-D 175

18 2 R1, R2 RES., Chip 10k 1/16W 5%, 0603 VISHAY, CRCW060310K0JNEA 350

19 3 R7, R8, R3 RES., Chip 1k 1/16W 5%, 0603 VISHAY, CRCW06031K00JNEA 525

20 6 R4, R9, R20, R21, R22, R23 RES., Chip 100Ω 1/16W 5%, 0402 VISHAY, CRCW0402100RJNED 1050

21 1 R5 RES., Chip 10Ω 1/16W 5%, 0603 VISHAY, CRCW060310R0JNEA 175

22 1 R6 RES., Chip 4.02k 1/16W 1%, 0603 VISHAY, CRCW06024K02FKED 175

23 8 R11, R16, R17, R18, R19, R27, R29,

R30

RES., Chip 4.99k 1/16W 1%, 0402 VISHAY, CRCW04024K99FKED 1400

24 4 R24, R25 ,R26, R31 RES., Chip 10k 1/16W 5%,0402 VISHAY, CRCW040210K0JNED 700

25 1 R28 RES., Chip 20k 1/16W 5%,0402 VISHAY, CRCW040220K0JNED 175

26 1 U1 I.C., LTC2757CLX, LQFP48LX LINEAR TECH., LTC2757CLX 175

27 1 U2 I.C., LT1012ACS8, SO8 LINEAR TECH., LT1012ACS8 175

28 1 U3 I.C., LTC2054CS5, SOT23-5 LINEAR TECH., LTC2054CS5 175

29 1 U4 I.C., LTC6240CS5, SOT23-5 LINEAR TECH., LTC6240CS5 175

30 1 U5 I.C., LT1360CS8, SO8 LINEAR TECH., LT1360CS8 175

31 0 U6 I.C., LTC6655AHMS8-5, MSOP8 OPT 0

32 1 U8 I.C., LT1236ACS8-5, SO8 LINEAR TECH., LT1236ACS8-5 175

32 4 U9, U10, U11, U12 I.C., 74VHC595MTC, TSSOP16 FAIRCHILD SEMI., 74VHC595MTCX 700

33 1 U13 I.C., NC7SZ14P5X, SC70-5 FAIRCHILD SEMI., NC7SZ14P5X 175

34 1 U14 I.C., Serial EEPROM, TSSOP8 MICROCHIP, 24LC025-I/ST 175

35 1 U15 I.C., LT1761ES5-5, SOT23-5 LINEAR TECH., LT1761ES5-5 175

36 1 U16 I.C., LT1964ES5-5, SOT23-5 LINEAR TECH., LT1964ES5-5 175

37 8 SHUNTS AS SHOWN ON ASSY DWG SHUNT, 0.079" CENTER SAMTEC, 2SN-BK-G 1400

38 4 MTG STAND-OFF, NYLON (SNAP ON), 0.50" TALL KEYSTONE, 8833 (SNAP ON) 700

39 2 STENCILS BOTH SIDES DC1485A-1 2

dc1485af

DEMO MANUAL DC1485A

SCHEMATIC DIAGRAM

D D

C C

B B

A A

NOTES: UNLESS OTHERWISE SPECIFIED

REF

REG

PARALLEL INTERFACE

1. ALL RESISTORS ARE IN OHMS, 0402.

ALL CAPACITORS ARE IN MICROFARADS, 0402.

2. INSTALL SHUNTS ON JUMPERS AS SHOWN.

EXT

0 10

-2.5 7.5

0-55

MANUAL SPAN CONTROL

-2.5 2.5

-10 10

0 5

S1S2

SPAN

DC1485A-2 * LTC2757CLX

Wednesday, July 29, 2009 11

KIM T.

LEO C.

18-BIT PARALLEL INPUT, CURRENT OUTPUT DAC WITH READBACK

SCHEMATIC

SIZE

DATE:

DWG NO. REV

SHEET OF

TITLE:

CONTRACT NO.

APPROVALS

DRAWN:

CHECKED:

APPROVED:

ENGINEER:

DESIGNER:

TECHNOLOGY

Fax: (408)434-0507

Milpitas, CA 95035

Phone: (408)432-1900

1630 McCarthy Blvd.

LTC Confidential-For Customer Use Only

CUSTOMER NOTICE

LINEAR TECHNOLOGY HAS MADE A BEST EFFORT TO DESIGNA

CIRCUIT THAT MEETS CUSTOMER-SUPPLIED SPECIFICATIONS;

HOWEVER, IT REMAINS THE CUSTOMER'S RESPONSIBILITYTO

VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL

APPLICATION. COMPONENT SUBSTITUTION AND PRINTED

CIRUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT

PERFORMANCE OR RELIABILITY. CONTACT LINEAR

TECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE.

THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGYAND

SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS.

VREF

READ

D11

D15

D13

D10

D17

D14

MSPAN

D12

CLR_

D14

VREF

VOUT

D12

UPD

D13

CLR_

WR_

READ

MSPAN

D16

D15

D11

D10

D_/S

D16

UPD

D_/S

WR_

S1 MSPAN

V+

+5V

V-

VCC

+5V

VCC

V-

V+

VCC

-5V

VCC

V+

V-

VCC

-5V -5V

C20

100pF

1206

LT1236ACS8-5

4 5

VIN

GND TRIM

VOUT

C41

10uF,25V

1206

C37

1uF

0603

25V

AMP V-

VOUT

R23 100

0603

SDI

0.1uF

100

JP2

HD2X3-079

R26

10K

R28

20K

C14

1uF

1206

U12

74VHC595MTC

SCLR

GND

SER

SCK

RCK

VCC

Q'H

LTC6655AHMS8-5

4 5

SHDN

VIN

GND

GND GND

VOUT_S

VOUT_F

GND

JP5

EXT

GND 1

RVOS

U10

74VHC595MTC

SCLR

GND

SER

SCK

RCK

VCC

Q'H

100

4.02K

0603

0.1uF

C23

100pF

R27

4.99K

C17

100pF

74VHC595MTC

SCLR

GND

SER

SCK

RCK

VCC

Q'H

10K

0603 C10

0.1uF

0603

BAT54C

1 3

U13

NC7SZ14P5X

2 4

E2 GND

C36

10uF,25V

1206

JP4

EXT

GND 1

100pF

1206

0.1uF

C29

0.1uF

C19

0.1uF

10K

0603

0.1uF

C11

0.1uF

U16

LT1964ES5-5

3SHDN

OUTGND

BYP C38

0.01uF

E6 VREF

R17

4.99K

R29

4.99K

SDO

R21 100

R31

10K

C31

0.1uF

C33

0.1uF

HD2X20-100

15 14

C13

10uF,25V

1206

BAT54C

1 3

JP3

HD2X3-079

5 6

LT1360CS8

C21

1206

OPT

0.1uF

C35

0.01uF

LTC6240CS5

HD2X7-079-MOLEX

MOSI/SDA

EESDA

V+

SCK/SCL

EEVCC

MISO

EESCL

EEGND

AUX

GND

1uF

0805

R20

100

C34

1uF

0603

25V

U11

74VHC595MTC

SCLR

GND

SER

SCK

RCK

VCC

Q'H

C28

100pF

0.1uF

REFADJ

R16

4.99K

C30

10uF,25V

1206

JP1

HD2X3-079

CS/

0603

R30

4.99K

C16

0603

OPT

LTC2757CLX

35 1

D13

D12

D11

D15

D14

RVOS

VDD

D10

D_/S

READ

WR_

UPD RINS

IOUT2F

IOUT1

RINF

MSPAN

GND

REFADJ

RCOM

REFF

REFS

ROFSF

ROFSS

RFBS

RFBF

IOUT2S

GND/IOUT3

CLR_

GND

D16

D17

C40

0.1uF

E7 VCC

CLK

LTC2054CS5

GND

C12

0.1uF

U14

24LC025-I /ST

SDA

VCCA0

VSS

SCL

BAT54C

1 3

R22 100

0603

C25

0.1uF

AMP V+

R24

10K

U15

LT1761ES5-5

3BYP

OUTVIN

GND

SHDN

C39

10uF,25V

1206

R25

10K

C15

0603OPT

OPT

C18

10uF,25V

1206

R18

4.99K

R11

4.99K

LT1012ACS8

R19 4.99K

dc1485af

DEMO MANUAL DC1485A

ASSEMBLY DRAWINGS

dc1485af

DEMO MANUAL DC1485A

ASSEMBLY DRAWINGS

dc1485af

DEMO MANUAL DC1485A

PCB LAYOUT AND FILM

Top Silkscreen Top Solder Paste

Top Solder Mask

dc1485af

DEMO MANUAL DC1485A

PCB LAYOUT AND FILM

Layer 1-Top Layer Layer 2-GND Plane 1

Layer 3- GND Plane 2 + PWR Traces

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