Intersil ZL2005P Manual de usuario

Description

The ZL2005P is an innovative mixed-signal

power management and conversion IC that

combines a compact, efficient, synchronous buck

controller, adaptive drivers and key power and

thermal management functions in a single

package. The ZL2005PEV4 platform allows

evaluation of the features in the highly-

configurable ZL2005P via the SMBus interface

using PMBus™commands. The PMBus

command set is accessed by using Zilker Labs

evaluation software from a PC running Microsoft

Windows.

This evaluation board is meant to enable rapid

evaluation of the functionality of the ZL2005P in

a 10 Amp configuration. It has been optimized for

ease of evaluation across a wide range of input

and output conditions. This ZL2005PEV4

platform is provided as a reference design.

Features

•PMBus control via SMBus

•Pin-strap selection for stand-alone operation

•VOUT settable from +0.8V to +3.3V

•RDS(ON) sensing

•Convenient power connection

•Onboard enable switch

•Power good indicator

•External temperature sensor

Target Specifications

This board has been designed for the following

conditions:

•VIN = 12V (Board range 4.5V to 13.2V)

•VOUT = 1.2V (Board range is 0.8V to 3.3V)

•IOUT = 0A - 10A

•FSW = 600kHz

•Output ripple: < 1%

•Dynamic response 3% (7.5A - 10A step load) @ 2.5V

•Temperature: 25°C

Figure 1. Block Diagram

ZL2005P

SMBus

POWER IN

POWER OUT

Address

select

ZL2005PEV4

2 ZL2005PEV4DSr1.0

Functional Description

The ZL2005PEV4 provides the circuit required

to demonstrate the features of the ZL2005P in a

10Amp configuration. The ZL2005PEV4 has a

functionally-optimized layout that allows highly-

efficient operation to its maximum output current

(See board picture in Figure 2). The input power

connection is provided through banana jack

terminals. Stand-alone operation of the ZL2005P

is achieved by factory installed pin-strap settings

and pre-configuration via PMBus commands.

PMBus protocol communication is performed

via a SMBus interface using an external USB to

SMBus adaptor. PMBus commands can be used

to modify the settings of the evaluation platform.

Figure 3 shows the ZL2005P circuit schematic.

The circuit consists of the ZL2005P power

conversion and management IC with its minimal

component count.

The input voltage connection is made at J1 which

is labeled VIN+/-. J2 is the output connector for

the output voltage, VOUT+/-. The VIN+/- and

VOUT+/- connections are rated to 10 A.

Figure 4 shows the ZL2005PEV4 interface

schematic. It contains various circuits that

interface to the ZL2005P’s circuit. The hardware

enable function is controlled by a toggle switch

(SW1) on the ZL2005PEV4 board. External

temperature is monitored from a 2N3904

transistor (Q3) connected to the XTEMP pin.

This external temperature is read with the

READ_TEMPERATURE_2 PMBus command.

The power good status is indicated by the PG

LED at D11. The PG LED indicates the correct

state of the power good signal when power is

applied to the ZL2005PEV4 board. The right

angle headers at opposite ends of the board (J10

and J11) are available to daisy chain multiple

boards. The SMBus and Enable signals are

passed between these connectors. All header pins

and switch positions are labeled on the

ZL2005PEV4 board’s silkscreen as shown in

Figure 5.

The ZL2005P SMBus address is set by the

jumper applied to J12. The SA1 pin is strapped

by an 11k resistor to ground. The J12 jumper

applies a different resistor to the SA0 pin to

achieve the indicated SMBus address settings.

Note that power must be cycled to set a new

address.

Refer to Figures 5 through 10 for component

placement and board layout. The board layout

has been optimized for two-sided component

area and thermal performance. For ZL2005P

circuit layout design considerations refer to

Zilker Labs Application Note AN10 (Reference

1 on page 21).

ZL2005PEV4

ZL2005PEV4DSr1.0 3

Operation

Stand-Alone Operation

The ZL2005PEV4 is easy to setup and operate. It

is configured, out of the box, to provide 1.2V at

10A from a 12V source. All input and output

connections should be made before turning the

input supply on.

When the input power supply is turned on, and

the enable switch is set to enable, the ZL2005P

will output the configured voltage. A load can

be applied to the output and the circuit can be

tested.

PMBus Operation

The ZL2005P utilizes the PMBus protocol. The

PMBus functionality can be accessed via USB

from a PC running the Zilker Labs Evaluation

software on a Windows-XP or Windows-

2000/NT operating system.

Install the Zilker Labs Evaluation software using

the CD included in the ZL2005PEV4 kit or

download it from the web at

www.zilkerlabs.com.

For PMBus operation, connect a USB/SMBus

adaptor (J2) to the EVB (J10). Apply a USB

cable between the USB/SMBus adaptor and the

PC. Connect the output of the ZL2005PEV4 to

the desired load. Then connect an appropriate

power supply to the input. Place the enable

switch in “DISABLE” and turn on the power.

Invoke the ZL2005P interface software.

The Zilker Labs Evaluation software allows

modification of all ZL2005P PMBus parameters.

Manually configure the ZL2005P with the

interface software or load a predefined

configuration from a configuration text file.

Use the mouse-over pop-ups for help with the

Zilker Labs Evaluation software. Refer to the

Zilker Labs Application Note AN13 (Reference

3 on page 21) for PMBus details.

The enable switch can then be moved to

“ENABLE” and the ZL2005P can be tested.

Alternatively, the PMBus commands

ON_OFF_CONFIG and OPERATION may be

used to manipulate the enable state.

Modifying the ZL2005PEV4

In order to design and test an alternative power

train circuit with the ZL2005P, choose a desired

operating conditions and power train. Enter the

selected power design parameters into Zilker

Labs’ PID calculation/simulation tool. The

results from the simulation tool provide

appropriate compensation values to configure the

new ZL2005P circuit. Apply the new power

train circuit to the evaluation board. Power the

board and invoke the evaluation software. Then

configure the new PID coefficients using the

“PMBus: Basic” command page or loading a

configuration text file with the new

compensation coefficients in it.

ZL2005PEV4

4 ZL2005PEV4DSr1.0

Quick Start Guide

Stand-alone Operation

1. Set enable switch (EN) to “DISABLE”

2. Apply load to VOUT+/VOUT-

3. Connect power supply to VIN+/VIN-

(supply turned off)

4. Turn power supply on

5. Set enable switch (EN) to “ENABLE”

6. Test ZL2005P operation

PMBus Operation

1. Insert the Zilker Labs Eval Software CD

2. Install the Eval Software by running

setup.exe from the ZL_Eval_Installer folder

on the CD.

3. Connect a USB/SMBus adaptor (J2) to the

EVB (J10)

4. Select a SMBus address with the jumper on

J12

5. Connect supplied USB cable from computer

to EVB

a. Upon first time connection, the Found

New Hardware Wizard will appear.

Select “No, Not this time” and click

b. Select “Install from a list or specific

location (Advanced)” and click Next

c. Select “Search the best driver in these

locations” and only select the “Search

removable media” option, then click

d. If you encounter a popup warning during

driver installation, click the “Continue

Anyway” button

6. Follow steps 1 - 4 under Stand-alone

Operation

7. Invoke “Zilker_Labs_Eval” from the Start

menu under Zilker Labs

8. Monitor and configure EVB using the

informative pages in the evaluation software

9. Test the ZL2005P operation

Figure 2. ZL2005PEV4 Evaluation Board

Connect input

voltage here Connect load

here

Connect SMBus

controller here Connect other

eval boards here

PG LED EN Switch Address select

ZL2005PEV4

ZL2005PEV4DSr1.0 5

Schematics

Figure 3. ZL2005P Circuit

Title

Size Document Number Rev

Sheet of

4301 WESTBANK DRIVE

BUILDING A, SUITE 100

AUSTIN, TEXAS 78746

ZILKER LABS, INC. CONFIDENTIAL AND PROPRIETARY

RSCH-ZL2005-016 2.1

SCHEMATIC, 10A POINT OF LOAD

12Tuesday, October 23, 2007

VOUT

DGND

SYNC

SA0

SA1

ILIM1

SCL

SDA

SALRT

FC0

FC1

SS0

SS1

VTRK

VSEN

ISENB 19

ISENA 20

GL 22

PGND 23

GH 25

BST 26

VR 21

VDD 27

V25 28

XTEMP 29

VADJ 30

MGN 31

EN 33

DLY0 34

DLY1 35

PG 36

ILIM0

UVLO

SW 24

CFG 32

SGND

ZL2005P

2N3904

VIN

ISENB

4.7uF

ISENA

GND_SIGNAL

VDD

Temperature Measurement

place near low side FET

CON2_Banana

VIN

SYNC

Optional

C12

0.1uF

47uF

6.3V

SA0

47uF

6.3V

C10

47uF

6.3V

VOUT

VTRK

VOUTmax set

to 3.3V

GND_SIGNAL

1uF

VSENSE

4.7uF

BST

V25

BSZ130

BSZ035 C6

47uF

6.3V

0.47uH

47uF

6.3V

SMBus Address

set by J12

(page 2)

BAT54

SCL

SDA

SALRT

GND

11k

16.2k

34.8k

VOUT

22uF

C11

0.1uF

ZL2005PEV4

6 ZL2005PEV4DSr1.0

Figure 4. ZL2005P Interface

C68

22uF

SDA

R1719.6k R1821.5k R1923.7k R2026.1k R2128.7k

VO 3

U10

MIC2920A-3.3BS

CON2_Banana

Place pullups near J11

D12

BAT54

To Next Rail

From Previous Rail

SYNC

EN_BUS

+Vi2c

D11

GRN

Q10

2N7002/SOT

R14

470

SALRT

Backside

+Vi2c

EN_BUS

Enable on PG_0

Enable Open

Enable on Bus

PG_0

SCL

Enable

Monitor

Disable

The reference designs contained in this document are for reference and example purpose only.

THE REFERENCE DESIGNS ARE PROVIDED "AS IS" AND "WITH ALL FAULTS" AND ZILKER

LABS DISCLAMES ALL WARRANTIES, WHETHER DIRECT, INDIRECT, CONSEQUENTIAL

(INCLUDING LOSS OF PROFITS), OR OTHERWISE, RESULTING FROMTHE REFERENCE

DESIGNS OR ANY USE THEREOF.

Any use of such reference designs is at your own risk and you agree to indemnify Zilker Labs

for any damages resulting from such use.

Title

Size Document Number Rev

Sheet of

4301 WESTBANK DRIVE

BUILDING A, SUITE 100

AUSTIN, TEXAS 78746

ZILKER LABS, INC. CONFIDENTIAL AND PROPRIETARY

RSCH-ZL2005-016 2

SCHEMATIC, Interface

22Tuesday, June 12, 2007

R15

10.0K

R11

10.0K

VOUT

J10

HEADER 5X2

SW1

SW_SPDT

C67

22uF

D10

STPS20L45CG

D-2PAK

C63

180uF

16V

R13

10.0K

R10

10.0K

J11

HEADER 5X2

R12

10.0K

+Vi2c

VIN

+Vi2c

SALRT

SDA

SCL VTRK

SYNC

SA0

JP1

This regulator allows stand alone operation when not

using a USB dongle. When no USB dongle is applied,

this regualtor is supplying Vi2c current thus

efficiency measurements will be affected.

Addr

0x20

0x21

0x22

0x23

0x24

3 4

5 6

7 8

910

J12

HEADER 5x2 PIN

VIN

ZL2005PEV4

ZL2005PEV4DSr1.0 7

Board Layout

Figure 5. PCB – Silk Screen Top

ZL2005PEV4

8 ZL2005PEV4DSr1.0

Figure 6. PCB – Top Layer

ZL2005PEV4

ZL2005PEV4DSr1.0 9

Figure 7. PCB – Inner Layer 1

ZL2005PEV4

10 ZL2005PEV4DSr1.0

Figure 8. PCB – Inner Layer 2

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