Intel X38 Manual de usuario

Document Number: 318469-002

Intel®X38 Express Chipset

Memory Technology and

Configuration Guide

White Paper

January 2008

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INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL®PRODUCTS. NO LICENSE, EXPRESS OR

IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT

AS PROVIDED IN INTEL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY

WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL

PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY,

OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended

for use in medical, life saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel

reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from

future changes to them.

The Intel®X38 Express Chipset MCH component may contain design defects or errors known as errata which may cause the

product to deviate from published specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Intel and the Intel logo are trademarks of Intel Corporation in the U.S. and other countries.

*Other names and brands may be claimed as the property of others.

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Contents

1Introduction.....................................................................................................5

2Technology Enhancements of Intel®Fast Memory Access (Intel®FMA) .....................6

2.1 Just in Time Command Scheduling............................................................6

2.2 Command Overlap..................................................................................6

2.3 Out of Order Scheduling..........................................................................7

2.4 Opportunistic Writes ...............................................................................7

3Supported Memory Technologies and Configurations..............................................8

3.1 Memory Technology Supported.................................................................8

3.2 DRAM Device Timing Support.................................................................10

3.3 ECC Support........................................................................................10

3.4 Valid Front Side Bus and Memory Speeds.................................................11

3.5 System Memory DIMM Configuration Support...........................................11

4Memory Organization and Operating Modes ........................................................12

4.1 Single-Channel Mode ............................................................................12

4.2 Dual Channel Modes .............................................................................12

4.2.1 Dual Channel Symmetric Mode..................................................12

4.2.2 Dual Channel Asymmetric Modes...............................................13

Tables

Table 3-1. Memory Technology Support Details.....................................................9

Table 3-2. DDR2 and DDR3 DRAM Device Timing Support.....................................10

Table 3-3. Intel®X38 Valid FSB/Memory Speed Configurations..............................11

Table 4-1. Sample Dual Channel Symmetric Organization Mode.............................13

Table 4-2. Sample Dual Channel Stacked Asymmetric Organization Mode................13

Table 4-3. Sample Dual Channel L-Shaped Asymmetric Organization Mode..............14

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Revision History

Revision

Number Description Revision

Date

-001 Initial release October 2007

-002 Corrected DDR3 DIMM Module Support

Added Configuration details January 2008

Introduction

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1Introduction

This document details the Intel®X38 Express Chipset system memory technology

enhancements, supported memory configurations, and memory organizations. It is

intended for a technical audience interested in learning about the performance

enhancements and simplified population rules offered by Intel®Fast Memory Access

and Intel®Flex Memory Technology in the platforms based on the Intel X38 Express

Chipset.

Technology Enhancements of Intel® Fast Memory Access (Intel® FMA)

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2Technology Enhancements of

Intel®Fast Memory Access

(Intel®FMA)

This chapter details Intel®X38 Express Chipset technology enhancements of its

memory controller known as Intel®Fast Memory Access (Intel®FMA). The memory

controller is located on the chipset’s 82X38 Memory Controller Hub (MCH) component.

With the growing reliance on faster and less latent memory technologies for today’s

high performance platforms, it has become necessary to not only increase system

memory transfer rate speeds, but to also streamline usage of the memory controller

protocol in novel and intelligent ways to decrease latency and optimize memory

bandwidth. To do this, several Intel technologies, known collectively as Intel®FMA,

have been included in this generation of Intel’s chipsets.

The following sections outline and explain the technology enhancements: Just In Time

Scheduling, Command Overlap, Out of Order Scheduling, and Opportunistic Writes.

2.1 Just in Time Command Scheduling

The Intel X38 Express Chipset has an advanced command scheduler where all pending

requests are examined simultaneously to determine the most efficient request to be

issued next. The most efficient request is picked from all pending requests and issued

to system memory Just In Time to make optimal use of Command Overlapping. Thus,

instead of having all memory access requests go individually through an arbitration

mechanism forcing requests to be executed one at a time, they can be started without

interfering with the current request allowing for concurrent issuing of requests. This

allows for the optimization of bandwidth and reducing of latency while retaining

system memory protocol.

2.2 Command Overlap

Command Overlap allows for the insertion of the DRAM commands between the

Activate, Precharge, and Read/Write commands normally used, as long as the inserted

commands do not affect the currently executing command. This allows for situations

where multiple commands can be issued in an overlapping manner, increasing the

efficiency of system memory protocol.

Technology Enhancements of Intel® Fast Memory Access (Intel® FMA)

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2.3 Out of Order Scheduling

Leveraging Just In Time Scheduling and Command Overlap, the Intel X38 Express

Chipset continuously monitors pending requests to system memory for the best use of

bandwidth and reduction of latency. If there are multiple requests to the same open

page, these requests would be launched in a back to back manner to make optimum

use of the open memory page. This ability to reorder requests on the fly allows the

Intel X38 Express Chipset to further reduce latency and increase bandwidth efficiency.

This is especially important for helping overcome the in-order manner of the Front

Side Bus between the Intel X38 Express Chipset and the processor to minimize

processor starvation.

2.4 Opportunistic Writes

Processor requests for memory reads usually are weighted more heavily than writes to

memory to avoid cases of starving the processor of data to process while the writes

are issued to system memory. Instead of having writes issued to a pending queue to

be flushed to memory when certain watermarks are reached, which could starve the

processor of data while it waits for the write flush to finish, the Intel X38 Express

Chipset monitors system memory requests and issues pending write requests to

memory at times when they will not impact memory read requests. This allows for an

almost continuous flow of data to the processor for processing.

Supported Memory Technologies and Configurations

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3Supported Memory

Technologies and

Configurations

3.1 Memory Technology Supported

The X38 Express Chipset supports the following DDR2 and DDR3 Data Transfer Rates,

DIMM Modules, and DRAM Device Technologies:

•DDR2 Data Transfer Rates:

⎯667 (PC2-5300) and 800 (PC2-6400)

•DDR3 Data Transfer Rates:

⎯800 (PC3-6400), 1067 (PC3-8500), and 1333 (PC3-10600)

•DDR2 DIMM Modules:

⎯Raw Card C - Single Sided x16 un-buffered non-ECC

⎯Raw Card D - Single Sided x8 un-buffered non-ECC

⎯Raw Card E - Double Sided x8 un-buffered non-ECC

⎯Raw Card F - Single Sided x8 un-buffered ECC

⎯Raw Card G - Double Sided x8 un-buffered ECC

•DDR3 DIMM Modules:

⎯Raw Card A - Single Sided x8 un-buffered non-ECC

⎯Raw Card B - Double Sided x8 un-buffered non-ECC

⎯Raw Card C - Single Sided x16 un-buffered non-ECC

•DDR2 and DDR3 DRAM Device Technology:

⎯512 Mb and 1 Gb

Supported Memory Technologies and Configurations

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Table 3-1. Memory Technology Support Details

Mem.

Type Raw

Card

Ver.

DIMM

Cap. DRAM

Device

Tech.

DRAM

Org. # of

DRAM

Devices

# of

Physical

Device

Ranks

# of

Row /Col

Address

Bits

# of

Banks

Inside

DRAM

Page

Size

256 MB 512 MB 32M X 16 4 1 13/10 4 8K

C 512 MB 1 GB 64M X 16 4 1 13/10 8 8K

512 MB 512 MB 64M X 8 8 1 14/10 4 8K

D 1 GB 1 GB 128M X 8 8 1 14/10 8 8K

1 GB 512 MB 64M X 8 16 2 14/10 4 8K

E 2 GB 1 GB 128M X 8 16 2 14/10 8 8K

512 MB 512Mb 64M X 8 9 1 14/10 4 8K

F 1 GB 1Gb 128M X 8 9 1 14/10 8 8K

1 GB 512Mb 64M X 8 18 2 14/10 4 8K

DDR2

667

and

800

G 2 GB 1Gb 128M X 8 18 2 14/10 8 8K

512 MB 512 MB 64M X 8 8 1 13/10 8 8K

A 1 GB 1 GB 128M X 8 8 1 14/10 8 8K

1 GB 512 MB 64M X 8 16 2 13/10 8 8K

B 2 GB 1 GB 128M X 8 16 2 14/10 8 8K

256 MB 512 MB 32M X 16 4 1 12/10 8 8K

DDR3

800,

1067,

and

1333 C 512 MB 1 GB 64M X 16 4 1 13/10 8 8K

Supported Memory Technologies and Configurations

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3.2 DRAM Device Timing Support

The X38 Express Chipset supports the following DDR2 and DDR3 DRAM Device Speed

Bin and Write Latency (WL) Timings on the main memory interface.

Table 3-2. DDR2 and DDR3 DRAM Device Timing Support

Memory

Type DRAM Data

Rate tCL t

RCD t

RP WL Units

667 MT/s 5 5 5 4 tCK

800 MT/s 5 5 5 4 tCK

DDR2

800 MT/s 6 6 6 5 tCK

800 MT/s 5 5 5 5 tCK

800 MT/s 6 6 6 5 tCK

1067 MT/s 7 7 7 6 tCK

1067 MT/s 8 8 8 6 tCK

1333 MT/s 8 8 8 7 tCK

1333 MT/s 9 9 9 7 tCK

DDR3

1333 MT/s 10 10 10 7 tCK

3.3 ECC Support

For DDR3 the X38 Express Chipset does NOT support ECC, does not support ECC un-

buffered DIMMs, and it does not support any memory configuration that mixes non-

ECC with ECC un-buffered DIMMs.

For DDR2 the X38 Express Chipset does support ECC and ECC un-buffered DIMMs but

it does NOT support any memory configuration that mixes non-ECC with ECC un-

buffered DIMMs.

See Section 3.1 for un-buffered DIMM support details.

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