Hyundai GMS800 Manual de usuario
NOV. 1996 Rev. 1.0
8-BIT SINGLE-CHIP MICROCOMPUTERS
GMS800 Series
Instruction Manual
Revision 1.0
Published by
MCU Application Team in HYUNDAI MicroElectronics Co., Ltd.
© HYUNDAI MicroElectronics Co., Ltd. 1996. All Right Reserved.
Additional information of this manual may be served by HYUNDAI MicroElectonics Offices in Korea or
Distributors and Representatives listed at address directory.
HYUNDAI MicroElectonics reserves the right to make changes to any Information here in at any time
without notice.
The information, diagrams, and other data in this manual are correct and reliable; however, HYUNDAI
MicroElectonics Co., Ltd. is in no way responsible for any violations of patents or other rights of the third
party generated by the use of this manual.
Table of Contents
1. ADDRESSING MODE..............................................................................................................1
1.1. Inherent Addressing Mode....................................................................................................................................2
1.2. Immediate Addressing Mode
#imm................................................................................................................3
1.3. Direct Page Addressing Mode
dp...................................................................................................................4
1.4. Absolute Addressing Mode
!abs...................................................................................................................5
1.5. Indexed Addressing Mode....................................................................................................................................6
1.6. Indirect Addressing Mode.....................................................................................................................................8
1.7. Relative Addressing Mode.................................................................................................................................. 11
1.8. Bit Manipulation Mode.......................................................................................................................................13
1.9. 16 Bit Operation Mode
dp.......................................................................................................................... 14
1.10. Etc.................................................................................................................................................................... 15
2. INSTRUCTION SET ..............................................................................................................17
3. APPENDIX..............................................................................................................................65
3.1. Instruction Map.................................................................................................................................................. 65
3.2. Alphabetic Order Table of Instruction.................................................................................................................66
3.3. Instruction Table by Function ............................................................................................................................. 71
Addressing Mode
1
1. ADDRESSING MODE
Addressing refers to the specification, within an instruction, of the location of the operand on which the
instruction will operate. Because G8MC core has no 16-bit register, other than the program counter, which
can be used to specify an address, it is necessary that G8MC core user understand the various addressing
modes. This gives the experienced programmer flexibility for writing programs that are more sufficient in the
number of instructions and the execution time.
This core has 10 addressing modes as shown bellows.
Inherent Addressing Mode
Immediate Addressing Mode
Direct Page Addressing Mode
Absolute Addressing Mode
Indexed Addressing Mode
Indirect Addressing Mode
Relative Addressing Mode
Bit Manipulation Mode
16-Bit Operation Mode
Etc.
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2
1.1. Inherent Addressing Mode
This is a mode that needs no address field at all. The operand is specified implicitly in the definition of the
operation code. This mode is used to instructions which operate on registers(A,X,Y,PSW,SP). This mode
has an important advantage that executes faster than any two- or three-byte instruction.
OP CODE
Register Instructions
A ASL DAA DAS DEC INC LSR PUSH POP ROL
ROR XCN
X INC PUSH POP
Y INC PUSH POP
A,X TAX TXA XAX
A,Y TAY TYA XAY MUL
X,Y XYX
X,SP TSPX TXSP
A,X,Y DIV
PSW CLRC CLRG CLRV DI EI PUSH POP SETC SETG
ETC. BRK NOP RET RETI STOP
Addressing Mode
3
1.2. Immediate Addressing Mode
#imm
The operand is specified in the instruction itself. In other word, an immediate mode instruction has an
operand field rather than an address field. Immediate mode instructions are useful for Initializing registers to
a constant value. Immediate data must be 8-bit data.
Register ( A,X,Y )
OP CODE #imm
Operand Instructions
A ADC AND CMP OR SBC EOR LDA
X CMPX LDX
Y CMPY LDY
Example)
04 35 ADC #35H
Memory(dp)
OP CODE #imm dp
Operand Instructions
Memory LDM
Example) (G=1)
E4 55 35 LDM 35H,#55H
Op code ( 04 )
Operand ( 35 )
MEMORY
A ←A+35h+C
Operand( 55 )
Opcode ( E4 )
data
Operand ( 35 )
MEMORY
data ←55h
0 Page
000h
0FFh
100h
135h
1FFh
0 Page
1 Page
immediate data
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1.3. Direct Page Addressing Mode
dp
The address field of the instruction gives the address of the operand in memory. The 2nd byte of instruction
is the offset from the start address of direct page. Direct Page(dp) is determined by G-flag.
G=0 0-Page ( !0000H ~ !00FFH) G=1 1-Page ( !0100H ~ !01FFH)
OP CODE dp
Operand Instructions
A ADC AND CMP LDA EOR OR SBC
X LDX CMPX
Y LDY CMPY
Memory ASL COM DEC INC LSR ROL ROR TST
Example) ( G=1 )
05 35 ADC 35H
Example) ( G=1 )
89 35 INC 35H
Op code ( 05 )
data
Operand ( 35 )
MEMORY
A ←A+data+C
0 Page
000h
0FFh
100h
135h
1FFh
0 Page
1 Page
Op code ( 89 )
data
Operand ( 35 )
MEMORY
data ←data + 1
0 Page
000h
0FFh
100h
135h
1FFh
0 Page
1 Page
Addressing Mode
5
1.4. Absolute Addressing Mode
!abs
The address field of the instruction gives the address of the operand in memory. 2nd byte instruction is the
lower address and 3rd byte is the upper address. The disadvantage of absolute addressing mode is to
require 3-byte instruction.
OP CODE Low Address Upper Address
Operand Instructions
A ADC AND CMP LDA EOR OR SBC STA
X CMPX LDX STX
Y CMPY LDY STY
PSW JMP CALL
Memory ASL BIT DEC INC LSR ROL ROR TCLR1 TSET1
Example)
07 35 D0 ADC !0D035H
Example) ( G=1 )
98 35 01 INC !0135H
Op code ( 07 )
Operand( 35 )
data
Operand( D0 )
MEMORY
A ←A+data+C
D035h
Op code ( 98 )
data
Operand ( 35 )
Operand ( 01 )
MEMORY
data ←data + 1
0 Page
000h
0FFh
100h
135h
1FFh
0 Page
1 Page
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X-Register
Y-Register
1.5. Indexed Addressing Mode
In the indexed addressing mode the contents of an index register(X,Y) is added to the address part of the
instruction to obtain the effective address. The index register contains an index value. The address field of
the instruction defines the beginning address of a data array in memory. Each operand in the array is stored
in memory relative to the beginning address. The distance between the beginning address and the address
of the operand is index value stored in the register.
X-register Indexed Addressing Mode in direct page(dp)
dp+X
The effective address is determined by adding the address of operand and the contents of X-register. it is
specified to direct page of memory.
OP CODE dp
Operand Instructions
A,Memory ADC AND CMP LDA EOR OR SBC STA ASL
DEC INC LSR ROL ROR XMA
Y,Memory LDY STY
Example) ( G=0, X=F5h)
06 45 ADC 45H+X
Y-register Indexed Addressing Mode in direct page
dp+Y
The effective address is determined by adding the address of operand and the contents of Y-register. it is
specified to direct page of memory.
OP CODE dp
Operand Instructions
X,Memory LDX STX
= 1 3A
+
Op code ( 06 )
Operand ( 45 )
data
X ( F5 )
MEMORY
A ←A+data+C
000h
0FFh
100h
03Ah
1FFh
0 Page
1 Page
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