Gan Systems GS66502B-EVBDB Manual de usuario

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This evaluation kit is designed for engineering evaluation in a controlled

lab environment and should be handled by qualified personnel ONLY.

High voltage will be exposed on the board during the test and even brief

contact during operation may result in severe injury or death.

Never leave the board operating unattended. After it is de-energized,

always wait until all capacitors are discharged before touching the board.

This product contains parts that are susceptible to damage by electrostatic

discharge (ESD). Always follow ESD prevention procedures when

handling the product.

The GS665XXX-EVBDB daughter board style evaluation kit consists of two GaN Systems 650V GaN

Enhancement-mode HEMTs (E-HEMTs) and all necessary circuits including half bridge gate drivers,

isolated power supplies and optional heatsink to form a functional half bridge power stage. It allows

users to easily evaluate the GaN E-HEMT performance in any half bridge-based topology, either with the

universal mother board (P/N: GS665MB-EVB) or users’ own system design for quick prototyping.

Serves as a reference design and evaluation tool as well as deployment-ready solution for easy in-

system evaluation.

Vertical mount style with height of 35mm, which fits in majority of 1U design and allows

evaluation of GaN E-HEMT in traditional through-hole type power supply board.

Current shunt position for switching characterization testing

Universal form factor and footprint for all products

The daughter board and universal mother board ordering part numbers are below:

Part Number

GaN E-HEMT P/N:

Description

GS66502B-EVBDB

GS66502B

GaN E-HEMT 650V/7.5A, 200mΩ

GS66504B-EVBDB

GS66504B

GaN E-HEMT 650V/15A, 100mΩ

GS66508B-EVBDB

GS66508B

GaN E-HEMT 650V/30A, 50mΩ

GS66508T-EVBDB

GS66508T

GaN E-HEMT top side cooled 650V/30A, 50mΩ

GS66516T-EVBDB

GS66516T

GaN E-HEMT top side cooled 650V/60A, 25mΩ

GS665MB-EVB

Universal 650V Mother Board

The daughter board GS665XXX-EVBDB circuit diagram is shown in Figure 1. The control logic inputs on

2x3 pin header J1 are listed below:

Descriptipon

ENA

Enable input. It is internally pulled up to VCC, a low logic disables all the PWM gate

drive outputs.

VCC

+5V auxillary power supply input for logic circuit and gate driver. On the daughter

board there are 2 isolated 5V to 9V DC/DC power supplies for top and bottom switches.

VDRV

Optional 9V gate drive power input. This pin allows users to supply separate gate drive

power supply. By default VDRV is connected to VCC on the daughter board via a 0 ohm

jumper FB1. If bootstrap mode is used for high side gate drive, connect VDRV to 9V

PWMH

High side PWM logic input for top switch Q1. It is compatible wth 3.3V and 5V

PWML

Low side PWM logic input for bottom switch Q2. It is compatible wth 3.3V and 5V

Logic inputs and gate drive power supply ground return.

The 3 power pins are:

VDC+: Input DC Bus voltage

VSW: Switching node output

VDC-: Input DC bus voltage ground return. Note that control ground 0V is isolated from VDC-.

Si8271 Iso.

Gate Driver Q1

Si8271 Iso.

Gate Driver

Iso. DC/DC

or Bootstrap

Iso. DC/DC

VDC+

VSW

VDC-

VCC

ENABLE

JP1

C4-10

PWMH

PWML

A. 2x GaN Systems 650V E-HEMT GS66508T(30A/50mΩ) or GS66516T (60A/25 mΩ). The PCB

footprints are universal and compatible for both packages

B. 5V-9V isolated DC/DC gate drive power supply

C. Decoupling capacitors C4-C11

D. Isolated gate driver Silab Si8271

E. Optional current shunt position JP1.

F. Test points for bottom Q2 VGS.

G. Recommended probing positions for Q2 VDS.

H. Holes for temperature monitoring of Q1/Q2

I. M3 mounting screw for heatsink

J. (Optional) RC snubber circuit

This daughter board includes two GaN Systems E-HEMT GS66508T (650V/30A, 50mΩ) or

GS66516T (650V/60A, 25mΩ) in a GaNPx™ Top cooled T type package, . The thermal pad on the

top of device is internally connected to the source. Electrical insulation will be needed for

heatsink attachment. GaNPx™ T package also features dual symmetrical gate for easier

paralleling and PCB layout.

Bipolar gate drive bias with +6V and -3V for turning off is chosen for this design for more robust

gate drive and better noise immunity.

5V-9V isolated DC/DC converters are used for gate drive. 9V is then splited into +6V and -3V bias

by using 6V Zener diode

By default gate drive supply input VDRV is tied to VCC +5V via 0Ωjumper (FB1). Remove FB1 if

separate gate drive input voltage is to be used.

Silab SI8271-GB-IS (3V UVLO) or SI8271–AB-IS (5V UVLO) isolated gate driver can be used for

this design. Both drivers are compatible with 6V/-3V gate drive and has CMTI dv/dt immunity

up to 200V/ns. It has separated source and sink drive outputs which eliminates the need for

additional diode.

GaN E-HEMT switching speed and slew rate can be directly controlled by the gate resistors. By

default the turn-on Rgate (R6/R12) is 10Ωand Rg_off (R7/R14) is 2Ω. User can adjust the values

of gate resistors to fine tune the turn-on and off speed.

FB1/FB2 are footprints for optional ferrite bead. By default they are populated with 0Ωjumpers.

If gate oscillation is observed, it is recommended to replace them with ferrite bead with Z=10-

20Ω@100MHz.

RS1/CS1 and RS2/CS2 are place holders to allow user to experiement with RC snubber circuit (not

installed). At high frequency operation the power dissipation for RS1/RS2 needs to be closely watched

and CS1/CS2 should be sized correctly. It is recommended to start with 33-47pF and 10-20Ω.

PS2

PES1-S5-S9-M

GND

VIN

2+VO 5

0V 4

VDRV

C14

4.7uF

C0805

VDDL_+6V

C15

4.7uF

C0805

GNDL

C16

4.7uF

C0805

3.3K

LED2

LED-0603

SI8271GB-IS

VDDI

GNDI

4GNDA 5

VO- 6

VO+ 7

VDD 8

PWML

DZ2

6.2V

SOD323-AC

R16

VEEL GNDL

C21

4.7uF

C0805

GNDL

C22

1uF GNDL

VEEL

JP1

CON-JMP-CSHUNT

R10

3.3K

R11

10R

PWML_IN

PGND

Q2S

Q2A

GS66508T

Q2B

GS66516T

ENABLE

Q2G2

R13

3.3K

Q2G

FB3

R12

10R

R14

Q2_GOUTQ2_VO+

RS2

10R

R1206

Q2_VO-

C17

1uF CS2

200p

C1206

DNP

VDDL_+6V

C18

1uF

VCC_+5V

The board provides an optional current shunt position JP1 between the source of Q2 and power

ground return. This allows drain current measurement for switching characterization test such as

Eon/Eoff measurement.

The JP1 footprint is compatible with T&M Research SDN series coaxial current shunt

(recommended P/N: SDN-414-10, 2GHz B/W, 0.1Ω)

If current shunt is not used JP1 must be shorted. JP1 affects the power loop inductance and its

inductance should be kept as low as possible. Use a copper foil or jumper with low inductance.

1. When measuring VSW with current shunt, ensure all channel probe grounds and current shunt

BNC output case are all referenced to the source end of Q2 before the current shunt. The

recommended setup of probes is shown as below.

2. The output of coaxial current shunt can be connected to oscilloscope via 50Ωtermination

impedance to reduce the ringing.

3. The measured current is inverted and can be scaled by using: Id=Vid/Rsense.

Current

Shunt

Q2 Source VDC-

1. GS66508T or GS66516T has a thermal pad at the top side for improved heat dissipation. Instead

of relying on PCB for cooling, the heat can be transferred to heatsink directly from the top

reducing the total thermal resistnace.

2. A heatsink can be mounted to the board using a M3 screw with lock washer and nylon insulated

bushing. Thermal Interface Material (TIM) is needed to provide electrical insulation and

conformance to the thermal pad surface. The daughter board evaluation kit supplies with a

35x35mm heatsink with M3 tapped hole, and other heatsinks can also be used to fit users’ system

design.

3. Care should be taken during the assembly of heatsink to avoid PCB bending and mechanical

stress to the GaN E-HEMT. We recommend to limit the torque of M3 mounting screw to <1 in-lb

(0.1Nm) for GS66508T and <2 in-lb (0.2Nm) for GS66516T, which translates to about ~50psi

pressure on each device.

4. To measure device case temperature, use IR camera or install thermocouple to monitor the

temperature through two drilled holes from the top side as shown below:

VGL

VSL

VSW

BNC case

To oscilloscope

probe input (use

50Ω termination)

BNC tip

VDS

VGS

5. The TIM we use on this assembly is Berguist®SilPad 1500ST, the measured total thermal

resistance can be found in Figure 9. Compared to bottom cooled design, T package eliminates the

PCB thermal resistance and significantly improve the thermal performance. Theraml grease is

typically not needed on the assembly. If thermal grease is to be applied, use non-conductive and

non-capacitive type thermal grease.

6. Forced air cooling is recommended for power testing.

GaNPX T GaNPX T

FR4 PCB

Heatsink

M3 Screw

Lock Washter

Insulated bushing

TIM

GaN Systems provides a universal 650V mother board (ordering part number: GS665MB-EVB, sold

separately) that can be used as the basic evaluation platform for all the daughter boards.

The universal 650V mother board evaluation kit includes following items:

1. Mother board GS665MB-EVB

2. 12VDC Fan

The board can be powered by 9-12V on J1. On-board voltage regulator creates to 5V for daughter board

and control logic circuits. J3 is used for external 12VDC fan.

12V INPUT

(+)5V Power Supply

CIN

VSW

PWM control & dead

time circuit

Daughter Board

Probing point for VSW

For Ext.

12VDC Fan

Airflow direction

Optional Cout

VDC- VOUT

VDC-

VDC+

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