5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Crestline DDRII Layout Guidelines
DDRII SignalGroups
Data
Group Signal Name
Control-to-Clock
Signal Group Minimum Length Maximum Length
Command-to-Clock
Strobe-to-Clock
Data-to-Strobe
Clock - 1.0"
Clock - 1.0"
Clock - 0.5"
Clock - 0.0"
Clock + 1.0"
Strobe - 220mils
8. Layout Guideline :
SA_DQ[63..0]/SB_DQ[63..0]
SA_DM[7..0]/SB_DM[7..0]
SA_DQS[7..0]/SA_DQS#[7..0]
SB_DQS[7..0]/SB_DQS#[7..0]
SA_RAS#/SB_RAS#
SA_BS[2..0]/SB_BS[2..0]
SA_MA[13..0]/SB_MA[13..0]Address
SA_CAS#/SB_CAS#
SA_WE#/SB_WE#
SM_CS#[3..0]Control SM_CKE[3..0]
SM_ODT[3..0]
Clock SM_CK[3..0]
SM_CK#[3..0]
SA_RCVENOUT#/SB_RCVENOUT#FeedBack SA_RCVENIN#/SB_RCVENIN#
Length Matching and Length Formulas
Clock + 1.0"
Strobe - 180mils
CLK group: SM_CK[3..0],SM_CK#[3..0]
GMCH
P1
P1
L0
L0
L1
L1
L2
L2
S1
S1
SO-DIMM
Topology
Reference Plane
Single Ended Trace Impedance
Differential Mode Impedance
Differential Pair Point-to-Point
Ground
42 +/- 15%
70 +/- 20%
Nominal Trace Width Inner Layer : 7 mils
Outer Layer : 8 mils
Outer Layer : 5 mils
Nominal CKto CK# Spacing
(edge to edge) Inner Layer : 4 mils
Minimum Serpentine Spacing Inner Layer : 12 mils
Outer Layer : 15 mils
Minimum Spacing to Other DDR2 Inner Layer : 16 mils
Outer Layer : 20 mils
Minimum Isolation Spacing to non-DDR2 25 mils
PackageLength Range- P1 1000 mils +/- 250 mils
Trace Length Limit - L0 Max =50 mils (Escape)
Trace Length Limit - L1 Max =500 mils (Breakout)
Stub Length S1-Stub from via to SO-DIMM Max =200 mils (Breakin)
MB Length Limits - L0 +L1 +L2 +S1 Min = 500 mils
Max = 4500 milsTotal Length - P1 +L0 +L1 +L2 +S1 Max = 4000 mils
Total Length for Channel A: X0
TotalLength for Channel B : X1
Maximim Via Count 2 (Per side)
SCK to SCK# Length Matching Match total length to within 5mils
Clock to Clock Length Match
(Total Length) Match Channel A clocks to X0 +/- 20mils
Match Channel A clocks to X1 +/- 20mils
Breakout Exceptions (Reduce geometries
for GMCHbreak-out region) Inner Layer : 4/12 mils to other DDR2
Outer Layer : 5/15 mils to other DDR2
Max. breakout length is 500 m ils
Breakin Exceptions (Reduce geometries
for SO-DIMM break-in region) CK to CK# spacing rule waived at
connector spacing of 15 mils to
other DDR2
Max. breakin length is 2 00 mils
Escape Breakout Breakin
4/4/12 7/4/16 8/5/15
Outer Layer : 5 mils
Inner Layer : 4mils spacing allowe d
L1
Inner Layer : 12 mils
55 +/- 15%
Max =500 mils (Breakout)
Max =50 mils (Escape)
Outer Layer : 10 mils
Point-to-Point with parallel termination
GMCH
Stub Length S1-Stub from via to SO-DIMM
MB Length Limits - L0 +L1 +L2 +S1 -
From GMCH ball to SO-DIMM pad
Trace Length Limit - L1
Package Length P1
Outer Layer : 15 mils
S1
Nominal Trace Width
Max =200 mils (Breakin)
8/5/15
Breakout
3
Total Length - P1 +L0 +L1 +L2 +S1 -
From GMCH die to SO-DIMM pad
Inner Layer : 4 mils
Maximim Via Count
Minimum CTRL Trace Spacing
7/4/16
Max. breakout length is 500 m ils
Min = 500 mils
25 mils
Topology
4/4/12
Max = 4500 mils
Inner Layer : 8 mils
Minimum Spacing to Other DDR2
L2
Reference Plane
Escape
(CLK-1.0") </= CTRL </= (CLK-0.0")
Max = 5000 mils
Ground
P1
750 mils +/- 200 mils
Minimum Isolation Spacing to non-DDR2
SO-DIMM
L0
Control group: SM_CKE[3..0],SM_CS#[3..0],SM_ODT[3..0]
Characteristic Trace Impedance
L3
CTRL to SCK/SCK # Length Matching
(Total Length including package)
Breakout Exceptions (Reduce geometries
for GMCHbreak-out region)
Trace Length Limit - L0
Vtt
Max = 1500 milsTrace Length L3
Parallel Termination Resistor 56 +/- 5%
Outer Layer : 5mils spacing allowed
P1
Max = 5000 mils
Minimum CMD Bus Trace Spacing
750 mils +/- 350 mils
Ground
Package Length P1
L3
Maximim Via Count
Total Length - P1 +L0 +L1 +L2 +S1 -
From GMCH die to SO-DIMM pad
Outer Layer : 10 mils
Min = 500 mils
CTRL to SCK/SCK # Length Matching
(Total Length including package)
Nominal Trace Width
4/4
L1
Max = 1500 mils
3
Max = 4500 mils
Trace Length L3
Breakout
Inner Layer : 6 mils
4/6,5/10
Max =200 mils (Breakin)
55 +/- 15%
Minimum Isolation Spacing to non-DDR2
Parallel Termination Resistor
Vtt
25 mils
Trace Length Limit - L0
Characteristic Trace Impedance
Topology
Outer Layer : 5 mils
SO-DIMM
GMCH
Reference Plane
L2
Trace Length Limit - L1
Point-to-Point with parallel termination
Escape
Inner Layer : 4 mils
Max =500 mils (Breakout)
(CLK-1.0") </= CM D </= (CLK+1.0")
Inner Layer : 12 mils
Max =50 mils (Escape)
Outer Layer : 15 mils
Stub Length S1-Stub from via to SO-DIMM
56 +/- 5%
S1
Minimum Spacing to Other DDR2
L0
Max. breakout length is 500 m ils
Outer Layer : 5mils spacing allowed
MB Length Limits - L0 +L1 +L2 +S1 -
From GMCH ball to SO-DIMM pad
Inner Layer : 4mils spacing allowe dBreakout Exceptions (R educe geometries
for GMCHbreak-out region)
Commandgroup:
SA_MA[13..0],SB_MA[13..0],SA_BS[2..0],SB_BS[2..0],SA_RAS#,
SB_RAS#,SA_CAS#,SB_CAS#,SA_WE#,SB_WE#
4/6,5/10
GMCH
Data group: SA_DQ[63..0],SB_DQ[63..0],SA_DM[7..0],SB_DM[7..0]
Reference Plane
Outer Layer : 5mils spacing allowed
L1
Minimum DQ Bus Trace Spacing
L2
Inner Layer : 6 mils
Max = 5000 mils
Min = 500 mils
Package Length P1
Breakout Exceptions (R educe geometries
for GMCHbreak-out region)
Minimum Isolation Spacing to non-DDR2
DQ/DM to DQS Length Matching
(Total Length including
package)
Max = 4500 mils
750 mils +/- 350 mils
4/4
Escape
25 mils
S1
Trace Length Limit - L0
Stub Length S1-Stubfrom via to SO-DIMM
Ground
P1 L0
MB Length Limits - L0 +L1 +L2 +S1 -
From GMCH ball to SO-DIMM pad
2
Outer Layer : 5 mils
SO-DIMM
Topology
Maximim Via Count
Breakout
Minimum Spacing to Other DDR2
Nominal Trace Width
Outer Layer : 8 mils
Trace Length L3
Max =500 mils (Breakout)
Outer Layer : 15 mils
Max =200 mils (Breakin)
Inner Layer : 12 mils
4/6
Total Length - P1 +L0 +L1 +L2 +S1 -
From GMCH die to SO-DIMM pad Max = 1500 mils
Point-to-Point
Max. breakout length is 500 mi ls
Max =50 mils (Escape)
Match DQ/DM to [SDQS - 200mils]
+/- 20mils, per byte lane
55 +/- 15%
Inner Layer : 4 mils
Trace Length Limit - L1
Characteristic Trace Impedance
Inner Layer : 4mils spacing allowed
Minimum Serpentine Spacing Same as DQ-to-DQ r outing
S1
Breakout Exceptions (R educe geometries
for GMCHbreak-out region)
Minimum Spacing to Other DDR2
P1
Match total length to within 5mils
Max =50 mils (Escape)
Differential Pair Point-to-Point
Max = 5000 mils
Max. breakin length is 2 00 mils
DQS to DQS# Length Matching
Trace Length Limit - L0
L2
Clock to Clock Length Match
(Total Length include package)
2 (Per side)
Ground
Min = 500 mils
DQS to DQS# spacing rule
waived at connector spacing of
10 mils to other DDR2
Outer Layer : 10 mils
SingleEnded Trace Impedance
Breakout
Max =200 mils (Breakin)
55 +/- 15%
Outer Layer : 5 mils
25 mils
Breakin
P1
Breakin Exceptions (Reduce geometries
for SO-DIMM break-in region)
750 mils +/- 350 mils
5/5/10
Data Strobe group: SA_DQS[7..0],SA_DQS[7..0]#,SB_DQS[7..0],SB_DQS[7..0]#
Escape
Stub Length S1-Stubfrom via to SO-DIMM
Differential Mode Impedance
L2
Max = 4500 mils
Inner Layer : 4 mils
SO-DIMM
Inner Layer : 8 mils
85 +/- 20%
Minimum Isolation Spacing to non-DDR2
GMCH
PackageLength Range- P1
4/4/12
Reference Plane
L1
S1
Inner Layer : 4 mils
Outer Layer : 15 mils
Max =500 mils (Breakout)
Nominal Trace Width
Nominal DQS to DQS# Spacing
(edge to edge)
Topology
Max. breakout length is 500 mi ls
Minimum Serpentine Spacing
L1
4/4/8
Inner Layer : 8mils to other DDR2
Inner Layer : 12 mils
L0
Trace Length Limit - L1
Maximim Via Count
Outer Layer : 5 mils
L0
Outer Layer : 10 mils to other DDR2
Outer Layer : 15 mils
Inner Layer : 12 milsMinimum DQS to DQ Spacin g
MB Length Limits - L0 +L1 +L2 +S1 -
From GMCH ball to SO-DIMM pad
Total Length - P1 +L0 +L1 +L2 +S1 -
From GMCH die to SO-DIMM pad
(CLK-0.5") </= D QS </= (CLK+1.0")
Feedback group:
SA_RCVENIN#],SA_RCVENOUT#,SB_RCVENIN#],SB_RCVENOUT#
These signals are routed internally on the GMCH package and don't require an y
routing on the MB. As a result, can be leftas NC.
SL SL MS
MS SLSL MS
SL/MSMS SL MS
SL/MS
SL/MS
SL MS
MS SL/MS
SLMS SL MS
4/4
DDRII Layout Guideline
0.1
5FL.,NO.300,Yang Guang St.,NeiHu
114 TAIPEI, TAIWAN,ROC
(886-2) 8751-8751
C
449Tuesday, November 18, 2008
Penryn+Candiga GM/PM45+ICH9M(VY050)
Title
Size Document Number Rev
Date: Sheet of
First International Computer,Inc.
