ESMT F25L04PA Series Manual de usuario

ESMT

F25L04PA (2D)

Elite Semiconductor Memory Technology Inc. Publication Date: Aug. 2012

Revision:1.4 1/33

Flash 3V Only 4 Mbit Serial Flash Memory

with Dual Output

FEATURES

Single supply voltage 2.3~3.6V

Standard, Dual SPI

Speed

- Read max frequency: 33MHz

- Fast Read max frequency: 50MHz; 86MHz; 100MHz

- Fast Read Dual max frequency: 50MHz / 86MHz

(100MHz / 172MHz equivalent Dual SPI)

Low power consumption

- Active current: 20 mA

- Standby current: 25 μA

- Deep Power Down current: 10 μA

Reliability

- 100,000 typical program/erase cycles

- 20 years Data Retention

Program

- Page programming time: 0.7 ms (typical)

Erase

- Chip erase time 1 sec (typical)

- Block erase time 0.15 sec (typical)

- Sector erase time 30 ms (typical)

Page Programming

- 256 byte per programmable page

SPI Serial Interface

- SPI Compatible: Mode 0 and Mode 3

End of program or erase detection

Write Protect ( WP )

Hold Pin ( HOLD )

All Pb-free products are RoHS-Compliant

ORDERING INFORMATION

Product ID Speed Package Comments

F25L04PA –50PG2D 50MHz

F25L04PA –86PG2D 86MHz

F25L04PA –100PG2D 100MHz

8-lead

SOIC 150 mil Pb-free

F25L04PA –50PAG2D 50MHz

F25L04PA –86PAG2D 86MHz

F25L04PA –100PAG2D 100MHz

8-lead

SOIC 200 mil Pb-free

F25L04PA –50HG2D 50MHz

F25L04PA –86HG2D 86MHz

F25L04PA –100HG2D 100MHz

8-contact

WSON 6x5 mm Pb-free

GENERAL DESCRIPTION

The F25L04PA is a 4Megabit, 3V only CMOS Serial Flash

memory device. The device supports the standard Serial

Peripheral Interface (SPI), and a Dual SPI. ESMT’s memory

devices reliably store memory data even after 100,000

programming and erase cycles.

The memory array can be organized into 2,048 programmable

pages of 256 byte each. 1 to 256 byte can be programmed at a

time with the Page Program instruction.

The device features sector erase architecture. The memory array

is divided into 128 uniform sectors with 4K byte each; 8 uniform

blocks with 64K byte each. Sectors can be erased individually

without affecting the data in other sectors. Blocks can be erased

individually without affecting the data in other blocks. Whole chip

erase capabilities provide the flexibility to revise the data in the

device. The device has Sector, Block or Chip Erase but no page

erase.

The sector protect/unprotect feature disables both program and

erase operations in any combination of the sectors of the

memory.

ESMT

F25L04PA (2D)

Elite Semiconductor Memory Technology Inc. Publication Date: Aug. 2012

Revision:1.4 2/33

PIN CONFIGURATIONS

8- Lead SOIC

(SOIC 8L, 150mil Body, 1.27mm Pin Pitch)

(SOIC 8L, 208mil Body, 1.27mm Pin Pitch)

1 8

2 7

3 6

4 5

VDD

HOLD

SCK

VSS

ESMT

F25L04PA (2D)

Elite Semiconductor Memory Technology Inc. Publication Date: Aug. 2012

Revision:1.4 3/33

8- Contact WSON

(WSON 8C, 6mmX5mm Body, 1.27mm Contact Pitch)

PIN DESCRIPTION

Symbol Pin Name Functions

SCK Serial Clock

To provide the timing for serial input and

output operations

SI Serial Data Input

To transfer commands, addresses or data

serially into the device.

Data is latched on the rising edge of SCK.

SO Serial Data Output

To transfer data serially out of the device.

Data is shifted out on the falling edge of

SCK.

CE Chip Enable To activate the device when CE is low.

WP Write Protect

The Write Protect ( WP ) pin is used to

enable/disable BPL bit in the status

HOLD Hold

To temporality stop serial communication

with SPI flash memory without resetting

the device.

VDD Power Supply To provide power.

VSS Ground

VSS

VDD

HOLD

SCK

ESMT

F25L04PA (2D)

Elite Semiconductor Memory Technology Inc. Publication Date: Aug. 2012

Revision:1.4 4/33

FUNCTIONAL BLOCK DIAGRAM

Address

Buffers

and

Latches

X-Decoder Flash

Y-Decoder

I/O Butters

and

Data Latches

Serial Interface

Control Logic

CE SCK SI WPSO HOLD

ESMT

F25L04PA (2D)

Elite Semiconductor Memory Technology Inc. Publication Date: Aug. 2012

Revision:1.4 5/33

SECTOR STRUCTURE

Table 1: F25L04PA Sector Address Table

Block Address

Block Sector

Sector Size

(Kbytes) Address range A18 A17 A16

127 4KB 07F000H – 07FFFFH

: : :

112 4KB 070000H – 070FFFH

1 1 1

111 4KB 06F000H – 06FFFFH

: : :

96 4KB 060000H – 060FFFH

1 1 0

95 4KB 05F000H – 05FFFFH

: : :

80 4KB 050000H – 050FFFH

1 0 1

79 4KB 04F000H – 04FFFFH

: : :

64 4KB 040000H – 040FFFH

1 0 0

63 4KB 03F000H – 03FFFFH

: : :

48 4KB 030000H – 030FFFH

0 1 1

47 4KB 02F000H – 02FFFFH

: : :

32 4KB 020000H – 020FFFH

0 1 0

31 4KB 01F000H – 01FFFFH

: : :

16 4KB 010000H – 010FFFH

0 0 1

15 4KB 00F000H – 00FFFFH

: : :

0 4KB 000000H – 000FFFH

0 0 0

ESMT

F25L04PA (2D)

Elite Semiconductor Memory Technology Inc. Publication Date: Aug. 2012

Revision:1.4 6/33

STATUS REGISTER

The software status register provides status on whether the flash

memory array is available for any Read or Write operation,

whether the device is Write enabled, and the state of the memory

Write protection. During an internal Erase or Program operation,

the status register may be read only to determine the completion

of an operation in progress. Table 2 describes the function of

each bit in the software status register.

Table 2: Software Status Register

Bit Name Function Default at

Power-up Read/Write

0 BUSY

1 = Internal Write operation is in progress

0 = No internal Write operation is in progress 0 R

1 WEL

1 = Device is memory Write enabled

0 = Device is not memory Write enabled 0 R

2 BP0 Indicate current level of block write protection (See Table 3) 0 R/W

3 BP1 Indicate current level of block write protection (See Table 3) 0 R/W

4 BP2 Indicate current level of block write protection (See Table 3) 0 R/W

5 TB Top / Bottom write protect 0 R/W

6 RESERVED Reserved for future use 0 N/A

7 BPL

1 = BP2,BP1,BP0 and TB are read-only bits

0 = BP2,BP1,BP0 and TB are read/writable 0 R/W

Note:

1. Only BP0, BP1, BP2, TB and BPL are writable.

2. BP0, BP1, BP2, TB and BPL are non-volatile.

3. All area are unprotected at power-on (BP2=BP1=BP0=0).

WRITE ENABLE LATCH (WEL)

The Write-Enable-Latch bit indicates the status of the internal

memory Write Enable Latch. If this bit is set to “1”, it indicates the

device is Write enabled. If the bit is set to “0” (reset), it indicates

the device is not Write enabled and does not accept any memory

Write (Program/ Erase) commands. This bit is automatically reset

under the following conditions:

• Power-up

• Write Disable (WRDI) instruction completion

• Page Program instruction completion

• Sector Erase instruction completion

• Block Erase instruction completion

• Chip Erase instruction completion

• Write Status Register instructions

BUSY

The Busy bit determines whether there is an internal Erase or

Program operation in progress. A “1” for the Busy bit indicates

the device is busy with an operation in progress. A “0” indicates

the device is ready for the next valid operation.

Top/Bottom Block Protect (TB)

The Top/Bottom bit (TB) controls if the Block-Protection (BP2,

BP1, BP0) bits protect from the Top (TB=0) or the Bottom (TB=1)

of the array as show in Table 3, The TB bit can be set with Write

Status Register (WRSR) instruction. The TB bit can not be written

to if the Block- Protection-Look (BPL) bit is 1 or WP is low.

ESMT

F25L04PA (2D)

Elite Semiconductor Memory Technology Inc. Publication Date: Aug. 2012

Revision:1.4 7/33

Table 3: F25L04PA Block Protection Table

Status Register Bit Protected Memory Area

Protection Level TB BP2 BP1 BP0 Block Range Address Range

0 X 0 0 0 None None

Upper 1/8 0 0 0 1 Block 7 070000H – 07FFFFH

Upper 1/4 0 0 1 0 Block 6~7 060000H – 07FFFFH

Upper 1/2 0 0 1 1 Block 4~7 040000H – 07FFFFH

Upper 6/8 0 1 0 1 Block 2~7 020000H – 07FFFFH

Upper 7/8 0 1 1 0 Block 1~7 010000H – 07FFFFH

Lower 1/8 1 0 0 1 Block 0 000000H – 00FFFFH

Lower 1/4 1 0 1 0 Block 0~1 000000H – 01FFFFH

Lower 1/2 1 0 1 1 Block 0~3 000000H – 03FFFFH

Lower 6/8 1 1 0 1 Block 0~5 000000H – 05FFFFH

Lower 7/8 1 1 1 0 Block 0~6 000000H – 06FFFFH

All Blocks X 1 0 0 Block 0~7 000000H – 07FFFFH

All Blocks X 1 1 1 Block 0~7 000000H – 07FFFFH

Block Protection (BP2, BP1, BP0)

The Block-Protection (BP2, BP1, BP0) bits define the size of the

memory area, as defined in Table 3, to be software protected

against any memory Write (Program or Erase) operations. The

Write Status Register (WRSR) instruction is used to program the

BP2, BP1, BP0 bits as long as WP is high or the Block-

Protection-Look (BPL) bit is 0. Chip Erase can only be executed if

Block-Protection bits are all 0. After power-up, BP2, BP1 and BP0

are set to 0.

Block Protection Lock-Down (BPL)

WP pin driven low (VIL), enables the Block-Protection-

Lock-Down (BPL) bit. When BPL is set to 1, it prevents any

further alteration of the TB, BPL, BP2, BP1, and BP0 bits. When

the WP pin is driven high (VIH), the BPL bit has no effect and its

value is “Don’t Care”. After power-up, the BPL bit is reset to 0.

ESMT

F25L04PA (2D)

Elite Semiconductor Memory Technology Inc. Publication Date: Aug. 2012

Revision:1.4 8/33

HOLD OPERATION

HOLD pin is used to pause a serial sequence underway with the

SPI flash memory without resetting the clocking sequence. To

activate the HOLD mode, CE must be in active low state. The

HOLD mode begins when the SCK active low state coincides

with the falling edge of the HOLD signal. The HOLD mode ends

when the HOLD signal’s rising edge coincides with the SCK

active low state.

If the falling edge of the HOLD signal does not coincide with the

SCK active low state, then the device enters Hold mode when the

SCK next reaches the active low state.

Similarly, if the rising edge of the HOLD signal does not

coincide with the SCK active low state, then the device exits in

Hold mode when the SCK next reaches the active low state. See

Figure 1 for Hold Condition waveform.

Once the device enters Hold mode, SO will be in high impedance

state while SI and SCK can be VIL or VIH.

If CE is driven active high during a Hold condition, it resets the

internal logic of the device. As long as HOLD signal is low, the

memory remains in the Hold condition. To resume

communication with the device, HOLD must be driven active

high, and CE must be driven active low. See Figure 22 for Hold

timing.

Active Hold Active Hold Active

HOLD

SCK

Figure 1: HOLD Condition Waveform

WRITE PROTECTION

The device provides software Write Protection.

The Write-Protect pin ( WP ) enables or disables the lock-down

function of the status register. The Block-Protection bits (BP2,

BP1, BP0, TB and BPL) in the status register provide Write

protection to the memory array and the status register. See Table

3 for Block-Protection description.

Write Protect Pin (WP )

The Write-Protect ( WP ) pin enables the lock-down function of

the BPL bit (bit 7) in the status register. When WP is driven low,

the execution of the Write Status Register (WRSR) instruction is

determined by the value of the BPL bit (see Table 4). When WP

is high, the lock-down function of the BPL bit is disabled.

Table 4: Conditions to Execute Write-Status-Register (WRSR)

Instruction

WP BPL Execute WRSR Instruction

L 1 Not Allowed

L 0 Allowed

H X Allowed

ESMT

F25L04PA (2D)

Elite Semiconductor Memory Technology Inc. Publication Date: Aug. 2012

Revision:1.4 9/33

INSTRUCTIONS

Instructions are used to Read, Write (Erase and Program), and

configure the F25L04PA. The instruction bus cycles are 8 bits

each for commands (Op Code), data, and addresses. Prior to

executing any Page Program, Write Status Register, Sector

Erase, Block Erase, or Chip Erase instructions, the Write Enable

(WREN) instruction must be executed first. The complete list of

the instructions is provided in Table 5. All instructions are

synchronized off a high to low transition of CE . Inputs will be

accepted on the rising edge of SCK starting with the most

significant bit. CE must be driven low before an instruction is

entered and must be driven high after the last bit of the instruction

has been shifted in (except for Read, Read ID, Read Status

transition on CE , before receiving the last bit of an instruction

bus cycle, will terminate the instruction in progress and return the

device to the standby mode.

Instruction commands (Op Code), addresses, and data are all

input from the most significant bit (MSB) first.

Table 5: Device Operation Instructions

Bus Cycle1~3

1 2 3 4 5 6 N

Operation Max.

Freq SIN S

OUT S

IN SOUT SIN SOUT SIN SOUT SIN SOUT S

IN S

OUT SIN SOUT

Read 33 MHz 03H Hi-Z A23-A16 Hi-Z A15-A8Hi-Z A7-A0Hi-Z X DOUT0 X DOUT1 X cont.

Fast Read13

50MHz

100 MH

0BH Hi-Z A23-A16 Hi-Z A15-A8Hi-Z A7-A0Hi-Z X X X DOUT0 X cont.

Fast Read Dual

Output11,12

50MHz

86 MHz

3BH A23-A16 A

15-A8A

7-A0X DOUT0~1 cont.

Sector Erase4 (4K Byte) 20H Hi-Z A23-A16 Hi-Z A15-A8Hi-Z A7-A0Hi-Z - - - - - -

Block Erase4, (64K Byte) D8H Hi-Z A23-A16 Hi-Z A15-A8Hi-Z A7-A0Hi-Z - - - - - -

Chip Erase 60H /

C7H Hi-Z - - - - - - - - - - - -

Page Program (PP)02H Hi-Z A23-A16 Hi-Z A15-A8Hi-Z A7-A0Hi-Z DIN0 Hi-Z DIN1 Hi-Z

Up to

256

bytes

Hi-Z

Read Status Register

(RDSR)6 05H Hi-Z X DOUT - - - - - - - - - -

Write Status Register

(WRSR)01H Hi-Z DIN Hi-Z - - -. - - - - - - -

Write Enable (WREN)9 06H Hi-Z - - - - - - - - - - - -

Write Disable (WRDI) 04H Hi-Z - - - - - - - - - - - -

Deep Power Down (DP) B9h Hi-Z - - - - - - - - - - - -

Release from Deep

Power Down (RDP) ABH Hi-Z - - - - - - - - - - - -

Read Electronic

Signature (RES)7 ABH Hi-Z X X X X X X X 12H - - - -

Jedec Read ID

(JEDEC-ID)8 9FH Hi-Z X 8CH X 30H X 13H - - - - - -

00H Hi-Z X 8CH X 12H - -

Read ID (RDID)10

50MHz

100MH

90H Hi-Z 00H Hi-Z 00H Hi-Z 01H Hi-Z X 12H X 8CH - -

Note:

1. Operation: SIN = Serial In, SOUT = Serial Out, Bus Cycle 1 = Op Code

2. X = Dummy Input Cycles (VIL or VIH); - = Non-Applicable Cycles (Cycles are not necessary); cont. = continuous

3. One bus cycle is eight clock periods.

4. Sector Earse addresses: use AMS -A12, remaining addresses can be VIL or VIH

Block Earse addresses: use AMS -A16, remaining addresses can be VIL or VIH

5. To continue programming to the next sequential address location, enter the 8-bit command, followed by the data to be

programmed.

6. The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE .

7. The Read-Electronic-Signature is continuous with on going clock cycles until terminated by a low to high transition on CE .

8. The Jedec-Read-ID is output first byte 8CH as manufacture ID; second byte 30H as memory type; third byte 13H as

ESMT

F25L04PA (2D)

Elite Semiconductor Memory Technology Inc. Publication Date: Aug. 2012

Revision:1.4 10/33

memory capacity.

9. The Write-Enable (WREN) instruction and the Write-Status-Register (WRSR) instruction must work in conjunction of each

other. The WRSR instruction must be executed immediately (very next bus cycle) after the WREN instruction to make both

instructions effective. WREN can enable WRSR, user just need to execute it. A successful WRSR can reset WREN.

10. The Manufacture ID and Device ID output will repeat continuously until CE terminates the instruction.

11. Dual commands use bidirectional IO pins. DOUT and cont. are serial data out; others are serial data in.

12. Dual output data:

=(D

), (D

)

=(D

), (D

)

OUT0

OUT1

13. Max Load capacitance is 15pF.

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