Epiq Solutions Sidekiq X2 Manual de usuario

Sidekiq X2/X4 PDK

FPGA Development Manual

Release 3.17.1

Jan 27, 2023

Epiq Solutions Proprietary

Table of Contents

1 Overview 1

1.1 About this Document ............................................. 1

1.2 Legal Considerations .............................................. 1

1.3 Proper Care and Handling ........................................... 1

1.4 Introduction .................................................. 1

1.5 Terms and Deﬁnitions ............................................. 2

2 FPGA Reference Design 3

2.1 Overview .................................................... 3

2.2 FPGA Top Level ................................................ 4

2.2.1 PCIE Module ............................................. 4

2.2.2 Timestamp Module .......................................... 5

2.3 The User Application ............................................. 5

2.3.1 User Application Interfaces ...................................... 6

2.3.1.1 User App I/Q Data Sample Clocks ............................. 6

2.3.1.2 System Clocks and Resets .................................. 7

2.3.1.3 System Control/Status Interface .............................. 7

2.3.1.4 Software Register Interface ................................. 8

2.3.1.5 Test Memory Interface .................................... 10

2.3.1.6 RFIC Control Interface .................................... 11

2.3.1.7 RFIC Receive Data Interface ................................. 12

2.3.1.8 RFIC Transmit Data Interface ................................ 13

2.3.1.9 Rx Transport DMA Interface ................................. 14

2.3.1.10 Tx Transport DMA Interface ................................. 14

2.3.2 User Register Interface Module ................................... 15

3 Building and Debugging 17

3.1 Reference Design ................................................ 17

3.2 Custom User Applications ........................................... 18

3.3 Building the Project .............................................. 18

3.3.1 Annapolis Micro Systems Build Steps for the wszkvup_vpx3u_iope_dram platform ....... 19

3.3.2 Annapolis Micro Systems Build Steps for the WB3XBM platform ................. 19

3.4 Programming the Flash ............................................ 20

3.5 Testing the Bitstream ............................................. 20

3.5.1 Using JTAG for Debug ........................................ 20

4 Appendix: Top Level RTL Design Information 21

4.1 JESD RTL and Mapping ............................................ 21

4.1.1 JESD RTL Hierarchy ......................................... 21

4.1.2 JESD I/Q Data Sample Clocks .................................... 21

References 22

Epiq Solutions Proprietary

List of Figures

2.1 Sidekiq X2/X4 Simpliﬁed Block Diagram ................................... 4

2.2 Sidekiq X2/X4 User Application Block Diagram ............................... 6

2.3 Register Write Interface Timing Diagram ................................... 9

2.4 Register Read Interface Timing Diagram (VAR_LATENCY_REG_RD=0) .................. 9

2.5 Register Read Interface Timing Diagram (VAR_LATENCY_REG_RD=1) .................. 10

2.6 Rx Data Interface Timing Diagram ...................................... 13

2.7 Rx FIFO Interface Timing Diagram ...................................... 14

3.1 Project Folder Hierarchy ............................................ 17

Epiq Solutions Proprietary

List of Tables

1.1 Terms and Deﬁnitions ............................................. 2

2.1 PCIE Module Conﬁguration Parameters .................................... 5

2.2 RFIC Data Port Channel Mapping ....................................... 6

2.3 User App RFIC Sample Clock Mapping .................................... 7

2.4 Clocks and Resets Interface .......................................... 7

2.5 System Control/Status Interface ........................................ 8

2.6 reg_rx<H> Field Description .......................................... 8

2.7 Software Register Interface .......................................... 9

2.8 JESD Transmit Test Memory Interface ..................................... 11

2.9 RFIC Control GPIO Interface .......................................... 12

2.10 RFIC Control SPI Interface ........................................... 12

2.11 RFIC Receive Data Interface .......................................... 13

2.12 RFIC Transmit Data Interface ......................................... 13

2.13 Receive Transport DMA Interface ....................................... 14

2.14 Transmit Transport DMA Interface ...................................... 15

2.15 User Registers .................................................. 16

3.1 Pre-build Reference Design Images ...................................... 17

Epiq Solutions Proprietary

Disclaimer

Epiq Solutions is disclosing this document (“Documentation”) as a general guideline for development. Epiq Solutions

expressly disclaims any liability arising out of your use of the Documentation. Epiq Solutions reserves the right, at

its sole discretion, to change the Documentation without notice at any time. Epiq Solutions assumes no obligation

to correct any errors contained in the Documentation, or to advise you of any corrections or updates. Epiq Solutions

expressly disclaims any liability in connection with technical support or assistance that may be provided to you in

connection with the Information.

THE DOCUMENTATION IS DISCLOSED TO YOU “AS IS” WITH NO WARRANTY OF ANY KIND. EPIQ SOLUTIONS

MAKES NO OTHER WARRANTIES, WHETHER EXPRESSED, IMPLIED, OR STATUTORY, REGARDING THE DOCU-

MENTATION, INCLUDING ANY WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR

NONINFRINGEMENT OF THIRD PARTY RIGHTS. IN NO EVENT WILL EPIQ SOLUTIONS BE LIABLE FOR ANY CON-

SEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTAL DAMAGES, INCLUDING ANY LOSS OF DATA OR

LOST PROFITS, ARISING FROM YOUR USE OF THE DOCUMENTATION.

All material in this document is Copyrighted by Epiq Solutions 2023. All trademarks are property of their respective

owners.

Epiq Solutions Proprietary

Revision History

Date Version Description

09/27/2017 3.7 Initial Release

02/28/2018 3.8.1 Update instructions for conﬁguring FPGA and other minor updates

06/07/2018 3.9.0 Clariﬁcation on versioning

08/23/2018 3.10.0 Add support for external GPS module.

Fix user_app timing constraints. Add support for Reference DAC SPI. Add iq multi-

pliers.

Move location of golden image.

First X4 release.

10/11/2018 3.10.1 Document change, Section 8.3, change -c 1 to -c 0

Fix Tx Late timestamp getting stuck where the data_rd_counter reset is not syn-

chronized to the Tx clock domain causing metastability and incorrect reset state for

data_rd_counter once the reset pulse goes low.

01/05/2019 3.11.0 PCIe ip block now has its boundary at the core_wrapper.

Add timing optimization looping to the build script.

Add manual trigger.

X2, added 245.76 Mhz ObsRx.

X4, added dual two channel phase coherent and four channel independent Rx modes.

Added single channel on dual JESD lane for ObsRx in anticipation of 491.52 MHz

ObsRx.

02/22/2019 3.11.1 X4, update timing constraints to support 250 Mhz

06/25/2019 3.12.0 Add supoort for high sample rate Tx where dual JESD lanes are required for a single

channel. Modiﬁed high speed ObsRx on X2 such that get two samples for clock.

Add decimator on channels Rx1/Rx2. For X4, all Rx sample clocks are now driven

from the same Rx clock source, all ObsRx sample clocks are now driven from the

same ObsRx clock source, and all Tx sample clocks are now driven from the same Tx

clock source.

Fix PCIe Tx when packet size is larger than FIFO size. Add frequency hopping control

logic.

Upgrade to Vivado 2017.4 from 2016.4.

Add iq swap mode. Added JESD Tx sample data memories to user_app.

10/04/2019 3.12.1 Minor changes to improve JESD synchronization.

Doubled the PCIe Rx FIFO size on X4 ObsRx ports to support 491.52 MHz sample

rates so that the Rx FIFO does not go full.

12/6/2019 3.13.0 Add support for User App GPIO control and user app RFIC SPI interface.

Add user_pdk_conﬁg.v parameter ﬁle.

X4 Only, Add support for transmitting via PCIe on Tx channels A1 and B1.

Add WBSTAR 100 ms delay when reconﬁuring the FPGA via ICAPE.

X4 Only, Double the Rx FIFO size to help with timestamp gaps at higher sample rates.

6/05/2020 3.13.1 X4 Only, Updates for RevC board testability.

X4 Only, Increase Rx and ObsRx FIFO depths.

X2 Only, update Rx packet header to v1.

8/02/2020 3.14.0 Fix dual Tx underrun reporting bug.

01/14/2021 3.14.1 Upgrade to 8 lane PCIe for HTG-K800 and HTG-K810.

Fix for starting/stopping streaming on a 1PPS edge.

04/06/2021 3.15.0 Fix Tx Timestamp dropped packets after late bug.

Fix JESD Tx bug.

continues on next page

Epiq Solutions

Proprietary LIST OF TABLES

Table 1 – continued from previous page

04/12/2021 3.15.1 Add bus_synch_ﬁfo to register interface of the decimators.

Fix missing timestamp reset related to clock crossing synchronization on the register

interface.

Add register reset capability.

Add BASELINE_VCS_STATUS register.

Add frc_sel_for_tx to be used in Tx timestamp mode.

X4 Only, Add FPGA TDD mode

01/27/2022 3.16.1 Fix Tx timestamp mode inter-packet bug.

Fix Tx 65,532 block size bug.

Remove extra ﬂop delay of user_meta and sys_meta so that they line up with ﬁrst

sample in packet.

Fix in PCIe Tx FIFO logic such that packet data is still correct even if user_app is not

constantly requesting data and there is gaps between blocks.

10/26/2022 3.17.1 Increase rx_dma_meta_ﬁfo sizes to increase throughput rate in Rx low latency mode.

X4 xcku115 Only, Add 1 ms POR to the x4 xcku115 (htgk8100 and htgk810) PCIe

module

X4 Only, Update JESD Rx path for deterministic latency

Epiq Solutions Proprietary

1 Overview

1.1 About this Document

This document provides the necessary details for developing FPGA applications for use with the SidekiqTM X2 or

SidekiqTM X4 multichannel RF transceiver card developed by Epiq Solutions [5]. It is provided with the purchase of

a SidekiqX2 or a SidekiqX4 Platform Development Kit.

1.2 Legal Considerations

The SidekiqX2 and SidekiqX4 are distributed all over the world. Each country has its own laws governing the

reception and/or transmission of radio frequencies. The user of the SidekiqX2 or SidekiqX4 and associated software

is solely responsible for insuring that it is used in a manner consistent with the laws of the jurisdiction in which it is

used. Many countries, including the United States, prohibit the reception and/or transmission of certain frequency

bands, or receiving certain transmissions without proper authorization. Again, the user is solely responsible for the

user’s own actions.

1.3 Proper Care and Handling

The SidekiqX2 or SidekiqX4 unit is fully tested by Epiq Solutions before shipment, and is guaranteed functional at

the time it is received by the customer, and ONLY AT THAT TIME. Improper use of the SidekiqX2 or SidekiqX4 unit

can cause it to become non-functional. In particular, a list of actions that may cause damage to the hardware include

the following:

• Handling the unit without proper static precautions (ESD protection) when the housing is removed or opened

• Inserting or removing the unit from a host system when power is applied to the host system

• Connecting a transmitter to an Rx port without proper attenuation

• Executing custom software and/or an FPGA bitstream that was not developed according to guidelines

The above list is not comprehensive, and experience with the appropriate measures for handling electronic devices

is required.

1.4 Introduction

The SidekiqTM X2 or SidekiqTM X4 Platform Development Kit (PDK) provides the ability for users to create their own

custom applications. This is accomplished by customizing software and/or the RTL code that conﬁgures the host

FPGA. This manual gives an overview of the FPGA reference design, with the intention of empowering the user to

build upon the design to create custom applications.

Detailed information about the software environment, including how to create custom software applications, can be

found in a separate document, the Sidekiq Software Development Manual [3], which can be downloaded from the

Epiq Solutions support website [2]

Epiq Solutions

Proprietary 1.5: Terms and Deﬁnitions

In addition, the details of the hardware itself and system design of the unit is outside the scope of this document. For

more details about the hardware, please download and review the Sidekiq X2 Hardware User’s Manual [4] or the

Sidekiq X4 Hardware User’s Manual [6]. It is strongly recommended that the user read this document thoroughly

before attempting to dive into FPGA development. It is also a requirement for the user to be experienced with

Xilinx® FPGA devices, design ﬂow and software tools, and in particular Vivado®.

This manual is meant to concisely describe the FPGA reference design, but it is important to spend time reviewing the

actual design (i.e. RTL source code, build scripts, constraint ﬁles, etc.) to fully understand the design. The sections

of the manual were intentionally created to align with the basic hierarchy of the design, and the source code itself is

commented and will act as a supplement to the information provided here.

1.5 Terms and Deﬁnitions

Table 1.1: Terms and Deﬁnitions

Term Deﬁnition

1PPS 1 Pulse Per Second

ADC Analog to Digital (A/D) converter

DAC Digital to Analog (D/A) converter

DSP Digital Signal Processing

FIFO First In First Out

FPGA Field Programmable Gate Array

FRC Free-running counter

I/Q In-Phase / Quadrature Phase

<H> Software channel handle

IP Intellectual Property

JESD204B A multigigabit serial data converter interface standard

MHz Megahertz

PC Personal Computer

PCIe PCI Express

PDK Platform Development Kit

RF Radio Frequency

RFIC RF Integrated Circuit (AD9371)

RTL Register Transfer Level

Rx Receive

SDK Software Development Kit

SDR Software Deﬁned Radio

SPI Serial Peripheral Interface

Tx Transmit

Epiq Solutions Proprietary

2 FPGA Reference Design

2.1 Overview

The SidekiqTM X2 or the SidekiqTM X4 PDK provides a complete FPGA reference design that enables a user to quickly

and efﬁciently create custom applications targeting SidekiqX2 or SidekiqX4 installed a compatible ThunderboltTM 3

chassis hosting a Xilinx® Kintex® UltrascaleTM family FPGA. The supported carriers and devices are listed in Table

3.1 of Section 3.1.

The unmodiﬁed reference design provides a full FPGA implementation to ﬂow raw Rx I/Q samples from up to three

ADC channels for the X2 (Rx1, Rx2, and ObsRx), and up to six for the X4 (Rx1, Rx2, and ObsRx from each RFIC)

to the host system processor and to transmit from the host up to two DAC channels (Tx1 and Tx2). The PCIe data

transport mode is used on the SidekiqX2 and SidekiqX4 platforms.

The Rx path transfers baseband I/Q samples which are received from an Analog Devices AD9371 RFIC that is located

on the SidekiqX2 FMC card or from two Analog Devices AD9379 RFICs that are located on the SidekiqX4 FMC card

via a JESD204B receive interface. These samples pass into a processing block which allows the user to process,

timestamp, and transfer the samples via a FIFO interface to a PCIe subsystem. In the reference design, the user

application processing block functions as a simple pass-through which timestamps and drives the PCIe FIFO with no

changes to the samples. The 16-bit I and 16-bit Q components are concatenated to form a 32-bit wide data bus.

On the Tx side, I/Q samples are ﬁrst transferred from the host system to FPGA over PCIe, then they are transferred

to the RFIC on the SidekiqX2 or SidekiqX4 FMC card via a JESD204B transmit interface. Similar to the receive side,

transmit data consists of 16-bit I and 16-bit Q to form a 32-bit wide data bus. In Fig. 2.1, orange design blocks are ip

modules and cannot be changed. Red blocks are available in RTL, but should not be modiﬁed. Yellow blocks should

not require modiﬁcation, but certain applications may necessitate changes. Green blocks are the intended targets

for user modiﬁcation, and most applications should only require changes to these green blocks. Please note that the

SidekiqX4 (not shown in the diagram) is the same as SidekiqX2 except that it has three additional channels (Rx1,

Rx2, and ObsRx) coming from the second RFIC chip and two additional JESD modules (JESD204 chC and chD) for

interfacing these channels to the user_app.

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