Epiq Solutions Sidekiq Z2 Manual de usuario
Sidekiq Z2 and Matchstiq Z3u FPGA
Development Manual
Version 3.16.2
Updated 03/10/22
Disclaimer
Epiq Solutions is disclosing this document (“Documentation”) as a general guideline or
development. Epiq Solutions expressly disclaims any liability arising out o your use o the
Documentation. Epiq Solutions reserves the right, at its sole discretion, to change the
Documentation without notice at any time. Epiq Solutions assumes no obligation to correct
any errors contained in the Documentation, or to advise you o any corrections or updates.
Epiq Solutions expressly disclaims any liability in connection with technical support or
assistance that may be provided to you in connection with the In ormation.
THE DOCUMENTATION IS DISCLOSED TO YOU “AS IS” WITH NO WARRANTY OF ANY
KIND. EPIQ SOLUTIONS MAKES NO OTHER WARRANTIES, WHETHER EXPRESSED,
IMPLIED, OR STATUTORY, REGARDING THE DOCUMENTATION, INCLUDING ANY
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR
NONINFRINGEMENT OF THIRD PARTY RIGHTS. IN NO EVENT WILL EPIQ SOLUTIONS
BE LIABLE FOR ANY CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR
INCIDENTAL DAMAGES, INCLUDING ANY LOSS OF DATA OR LOST PROFITS, ARISING
FROM YOUR USE OF THE DOCUMENTATION.
All material in this document is Copyrighted by Epiq Solutions 2022. All trademarks are
Sidekiq Z2 and Matchstiq Z3u FPGA Development
Manual
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property o their respective owners.
Sidekiq Z2 and Matchstiq Z3u FPGA Development
Manual
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Revision Histor
Date Revision Description
06/06/2018 3.9.0 Initial release.
09/10/2018 3.10.0 FPGA builds are now built as part o the top level project Linux build
process. Add basic Tx capability.
12/12/2018 3.10.0 Document updates only. Update to section 8.2.1, added instructions on
how to obtain the actual schematic in Vivado or Figure 5, and added in o
about user_app reg x8708. Update build instructions.
04/25/2019 3.12.0 Add requency hopping control logic. Upgrade to Vivado 2018.2.
Add iq swap mode.
09/09/2019 3.12.0 Doc update only, update in o about pga programming.
01/14/2021 3.14.1 Fix FIFO ull write bug which resulted in the Rx header and sample data
to be scrambled in certain circumstances.
Fix bug where Rx would enter packed mode when not requested which
resulted in the timestamp being o by 338 counts and the data scrambled
as i it were in packed mode.
Fix or starting/stopping streaming on a 1PPS edge.
04/12/2021 3.15.1 Z3u: Add GPS_CONTROL_MASK read only register.
Z3u: Add gps_pps mux control.
All: Fix missing timestamp reset related to clock crossing synchronization
on the register inter ace.
All: Add register reset capability.
All: Add BASELINE_VCS_STATUS register.
All: Add rc_sel_ or_tx to be used in Tx timestamp mode.
10/29/2021 3.15.1
Updated
10/29/21
Documentation update only relating to pga programming and packed
mode not being available on the Z plat orms.
03/10/2022 3.16.2 Z3u: Add board_id to the FPGA_REG_VERSION register or Zu3 RevD.
Sidekiq Z2 and Matchstiq Z3u FPGA Development
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Table of Contents
1 About this Document..........................................................................................................................8
2 Legal Considerations.........................................................................................................................8
3 Proper Care and Handling.................................................................................................................8
4 Introduction........................................................................................................................................ 9
5 Re erences...................................................................................................................................... 10
6 Terms and De initions......................................................................................................................10
7 FPGA Re erence Design..................................................................................................................12
7.1 Overview.................................................................................................................................. 12
7.2 Top Level..................................................................................................................................13
7.3 user_app.................................................................................................................................. 14
7.3.1 user_app Signals.............................................................................................................. 15
7.3.2 Rx Path Inputs to user_app..............................................................................................16
7.3.3 Outputs rom user_app.....................................................................................................17
7.3.4 user_app Tx Inter ace.......................................................................................................18
7.3.5 user_reg_i ........................................................................................................................ 18
7.4 reg_i / user_reg_i ...................................................................................................................19
7.5 iio_data_i ................................................................................................................................. 20
7.6 timestamp_block......................................................................................................................20
7.7 gpio/uart................................................................................................................................... 21
7.8 system_wrapper.......................................................................................................................22
7.8.1 Sidekiq Z2 system_wrapper..............................................................................................22
7.8.2 Matchstiq Z3u system_wrapper........................................................................................22
8 Building and Debugging................................................................................................................... 26
8.1 Building a user_app..................................................................................................................26
8.1.1 Sidekiq Z2 Re erence Design...........................................................................................26
8.1.2 Matchstiq Z3u Re erence Design......................................................................................26
8.1.3 Custom user_apps............................................................................................................27
8.2 Building the project and bitstream............................................................................................27
8.3 Build with Linux........................................................................................................................ 28
8.3.1 Building Sidekiq Z2...........................................................................................................28
8.3.2 Building Matchstiq Z3u......................................................................................................28
8.4 Build with Windows..................................................................................................................29
8.5 Programming............................................................................................................................ 29
8.5.1 Programming the Sidekiq Z2 FPGA..................................................................................29
8.5.2 Programming the Matchstiq Z3u FPGA............................................................................29
8.6 Testing the Bitstream................................................................................................................ 29
8.7 Using JTAG or Debug.............................................................................................................29
Sidekiq Z2 and Matchstiq Z3u FPGA Development
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Table of Figures
Figure 1: Sidekiq Z2 Simpli ied Block Diagram....................................................................................13
Figure 2: User App Block Diagram.......................................................................................................14
Figure 3: Sample Timing Diagram........................................................................................................17
Figure 4: Sample User App to IIO Diagram..........................................................................................18
Figure 5: Sidekiq Z2 Zynq Processing System....................................................................................25
Sidekiq Z2 and Matchstiq Z3u FPGA Development
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Table of Tables
Table 1: Terms and De initions.............................................................................................................11
Table 2: Rx Control Register................................................................................................................15
Table 3: User Registers........................................................................................................................19
Sidekiq Z2 and Matchstiq Z3u FPGA Development
Manual
1 About this Document
This document provides the necessary details or developing FPGA applications on the SidekiqTM Z2
SDR or the Matchstiq Z3u SDR developed by Epiq Solutions [1]. It is provided with the purchase o a
Sidekiq Z2 Plat orm Development Kit or a Matchstiq Z3u Plat orm Development Kit.
2 Legal Considerations
Sidekiq or Matchstiq radio cards are distributed all over the world. Each countr has its own
laws governing the reception and/or transmission of radio frequencies. The user of Sidekiq or
Matchstiq radio cards and associated software is solel responsible for insuring that it is used
in a manner consistent with the laws of the jurisdiction in which it is used. Man countries,
including the United States, prohibit the reception and/or transmission of certain frequenc
bands, or receiving certain transmissions without proper authorization. Again, the user is
solel responsible for the user's own actions in using Sidekiq or Matchstiq radio cards and
other Epiq Solutions' products.
3 Proper Care and Handling
Each unit is ully tested by Epiq Solutions be ore shipment, and is guaranteed unctional at the time it
is received by the customer, and ONLY AT THAT TIME. Improper use o the Sidekiq or Matchstiq unit
can cause it to become non- unctional. In particular, a list o actions that may cause damage to the
hardware include the ollowing:
•Handling the unit without proper static precautions (ESD protection) when the housing is
removed or opened up
•Inserting or removing Sidekiq or Matchstiq rom a host system when power is applied to the
host system
•Connecting a transmitter to the RX port without proper attenuation – see the Speci ications
section or details on maximum RF signal input levels
•Executing custom so tware and/or an FPGA bitstream that was not developed according to
guidelines
The above list is not comprehensive, and experience with the appropriate measures or handling
electronic devices is required.
Sidekiq Z2 and Matchstiq Z3u FPGA Development
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4 Introduction
The Sidekiq and Matchstiq Plat orm Development Kit (PDK) provides the ability or users to create
their own custom applications. This can be accomplished by customizing so tware or the RTL code
that con igures the FPGA. This manual gives an overview o the FPGA re erence design, with the
intention o empowering the user to build upon the design to create custom applications.
This document describes the unctionality o the Sidekiq and Matchstiq PDK re erence design that
was/is designed, developed, and supported by Epiq Solutions. The standard Sidekiq Z2 Evaluation
Kit (EVK) bitstream was/is designed, developed, and supported by Analog Devices' Industrial I/O (IIO)
and their open source ecosystem. Documentation and support or the IIO design is not provided by
Epiq Solutions. The Sidekiq Z2 PDK re erence design and the Matchstiq Z3u re erence design does,
however, utilize certain critical components rom the Analog Devices' IIO design, and details or
building both the EVK (Sidekiq Z2 only) and PDK components to achieve a inal bitstream is described
in Section 8.
Detailed in ormation about the so tware environment, including how to create custom so tware
applications, can be ound in a separate document, the Sidekiq So tware Development Manual [2],
which can be downloaded rom the Epiq Solutions support website
(http://www.epiqsolutions.com/support [3]).
In addition, the details o the hardware itsel and system design o the unit is outside the scope o this
document. For more details about the hardware, please download and review the Sidekiq Z2
Hardware User's Manual [4] or the Matchstiq Z3U Hardware User's Manual [6]. It is strongly
recommended that the user read these documents thoroughly be ore attempting to dive into FPGA
development.
This manual is meant to concisely describe the FPGA re erence design, but it is important or even an
experienced developer to spend time evaluating the actual design (i.e. RTL source code), perhaps
even while digesting the in ormation presented here. The sections o the manual were intentionally
created to align with the basic hierarchy o the design, and the source code itsel is commented and
will act as a supplement to the in ormation provided here.
Sidekiq Z2 and Matchstiq Z3u FPGA Development
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5 References
[1] Epiq Solutions Website
https://epiqsolutions.com
[2] SDK Documentation
Sidekiq_Software_Development_Manual_for_x.xx.x.pdf
Available at: https://epiqsolutions.com/support
[3] Epiq Solutions Support Website
https://epiqsolutions.com/support
[4] Sidekiq Z2 Hardware User's Manual
Sidekiq_Z2_Hardware_Users_Manual_vx.x.pdf
Available at: https://epiqsolutions.com/support
[5] Analog Devices, Inc. IIO and Support
www.analog.com
[6] Matchstiq Z3u Hardware User Manual
Epiq-Solutions-Matchstiq-Z3u-Hardware-User-Manual_vx.x.pdf
Available at: https://epiqsolutions.com/support
[7] Sidekiq Z2 Getting Started Guide
Z2 Getting Started Guide.pdf
https://epiqsolutions.com/support
Sidekiq Z2 and Matchstiq Z3u FPGA Development
Manual
10
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