INTRODUCTION
1.1MARKETING CRAP.........................................................................................................................................................48
1.1.1Features.................................................................................................................................................................48
1.1.2Description............................................................................................................................................................49
2VIRTEX 5 ............................................................................................................................................................................50
3CONFIGURATION SECTION.........................................................................................................................................50
3.1CONFIGURATION SECTION FEEDBACK..........................................................................................................................51
3.2FPGA CONFIGURATION ................................................................................................................................................52
3.3USB AND PCI INTERFACES ...........................................................................................................................................53
3.4COMPACTFLASH INTERFACE.........................................................................................................................................53
3.4.1Main.txt .................................................................................................................................................................54
3.4.2Hardware ..............................................................................................................................................................57
3.5CONFIGURATION REGISTERS.........................................................................................................................................57
3.5.1Undocumented controls ........................................................................................................................................58
3.6FIRMWARE.....................................................................................................................................................................58
4CLOCK NETWORK..........................................................................................................................................................59
4.1.1GC Pins.................................................................................................................................................................59
4.2GLOBAL CLOCKS...........................................................................................................................................................59
4.3G0, G1, G2 CLOCKS ......................................................................................................................................................60
4.3.1Clock Synthesizers.................................................................................................................................................61
4.3.2Possible Outputs....................................................................................................................................................61
4.3.3Duty Cycle.............................................................................................................................................................62
4.3.4Jitter ......................................................................................................................................................................62
4.4EXT CLOCKS..................................................................................................................................................................62
4.4.1EXT0......................................................................................................................................................................62
4.4.2EXT1......................................................................................................................................................................63
4.4.3Daughtercard zero-delay mode ............................................................................................................................63
4.4.4SMA input..............................................................................................................................................................63
4.5PCI CLOCK ....................................................................................................................................................................64
4.6NON-GLOBAL CLOCKS..................................................................................................................................................64
4.6.1Clock TP................................................................................................................................................................64
4.6.2Ethernet Clock.......................................................................................................................................................65
4.6.3DDR2 Clocks.........................................................................................................................................................65
4.6.4SMA Clock A .........................................................................................................................................................66
5TEST POINTS.....................................................................................................................................................................66
5.1POWER THRU-HOLE.......................................................................................................................................................67
5.2POWER TP......................................................................................................................................................................68
5.3DIMM POWER...............................................................................................................................................................68
5.4“GC” TEST POINTS ........................................................................................................................................................69
5.5CLOCK TEST POINTS......................................................................................................................................................70
5.6DIMM SIGNALS.............................................................................................................................................................71
6USB INTERFACE ..............................................................................................................................................................71
6.1CONNECTING TO THE DN9002K10PCI.........................................................................................................................72
6.1.1Windows XP ..........................................................................................................................................................72
6.1.2Windows Vista.......................................................................................................................................................72
6.1.3Linux......................................................................................................................................................................72
6.1.4Communication.....................................................................................................................................................72
6.2VENDOR REQUESTS.......................................................................................................................................................72
6.2.1VR_CLEAR_FPGA ...............................................................................................................................................73
6.2.2VR_SETUP_CONFIG...........................................................................................................................................74
6.2.3VR_END_CONFIG...............................................................................................................................................74
6.2.4VR_SET_EP6TC (Read buffer size)......................................................................................................................74
6.2.5VR_MEM_MAPPED (Configuration Registers)..................................................................................................74
6.2.6Other Vendor Requests.........................................................................................................................................74
6.3MAIN BUS ACCESSES.....................................................................................................................................................74
6.3.1Important Note About Endpoints..........................................................................................................................75
6.3.2Performance..........................................................................................................................................................75
6.4FPGA CONFIGURATION ................................................................................................................................................76
6.4.1Readback...............................................................................................................................................................76
6.5USB HARDWARE...........................................................................................................................................................77
6.5.1Cypress CY7C68013A...........................................................................................................................................77
