Cronologic Ndigo5G-8 Manual de usuario

Revision 1.0.8 as of 2018-11-19

Firmware 2 (build 4865), Driver v1.3.0

cronologic GmbH & Co. KG

Ndigo5G-8

Ndigo5G-10

User Guide

cronologic

Contents

1 Introduction 1

1.1 Features ......................................... 1

2 Hardware 3

2.1 Installing the Board .................................. 3

2.2 Ndigo5G External Inputs and Connectors ...................... 4

2.2.1 Connectors ................................... 4

2.2.2 Analog Inputs ................................. 5

2.2.3 Digital Inputs .................................. 6

2.3 Extension Card ..................................... 7

2.4 Ndigo5G Functionality ................................. 8

2.4.1 ADC Modes ................................... 8

2.4.2 Zero Suppression ................................ 10

2.4.3 Trigger Blocks ................................. 10

2.4.4 Gating Blocks .................................. 15

2.4.5 Auto Triggering Function Generator ..................... 18

2.4.6 Timestamp Channel .............................. 18

2.4.7 Data Lookup Table ............................... 19

2.5 Multiple Ndigo boards synchronization ........................ 19

2.5.1 Calibration Procedure ............................. 20

2.5.2 Synchronizing a Ndgio5G and an HPTDC8-PCI .............. 22

2.6 Performing a ﬁrmware update ............................. 22

2.7 Calibrating the TDC .................................. 23

3 Driver Programming API 25

3.1 Constants ........................................ 25

3.2 Initialization ...................................... 25

3.2.1 Structure ndigo init parameters ........................ 25

3.3 Status Information ................................... 27

3.3.1 Functions for Information Retrieval ...................... 27

3.3.2 Structure ndigo static info ........................... 27

3.3.3 Structure ndigo param info .......................... 29

3.3.4 Structure ndigo fast info ............................ 29

3.3.5 Structure ndigo slow info ........................... 30

3.4 Conﬁguration ...................................... 30

3.4.1 Structure ndigo conﬁguration ......................... 31

3.4.2 Structure ndigo trigger ............................. 33

3.4.3 Structure ndigo trigger block ......................... 34

3.4.4 Structure ndigo gating block ......................... 36

3.4.5 Structure ndigo extension block ........................ 37

3.4.6 Run Time Control ............................... 37

3.5 Readout ......................................... 38

3.5.1 Input Structure ndigo read in ......................... 38

3.5.2 Input Structure ndigo read out ........................ 38

Contents

3.6 Other Functions .................................... 38

3.6.1 LED control ................................... 38

4 Packet Format 41

4.0.1 Output Structure ndigo packet ........................ 41

5 C Example 43

6 Technical Data 45

6.1 Digitizer Characteristics ................................ 45

6.1.1 1-Channel-Mode (5Gsps) ........................... 45

6.1.2 2-Channel-Mode (2.5 Gsps) .......................... 45

6.1.3 4-Channel-Mode (1.25 Gsps) ......................... 46

6.2 Electrical Characteristics ............................... 46

6.2.1 Oscillator .................................... 46

6.2.2 Environmental Conditions for Operation ................... 46

6.2.3 Environmental Conditions for Storage .................... 46

6.2.4 Power Supply .................................. 47

6.2.5 Analog Input .................................. 47

6.3 Information Required by DIN EN 61010-1 ...................... 47

6.3.1 Manufacturer .................................. 47

6.3.2 Intended Use and System Integration .................... 48

6.3.3 Cooling ..................................... 48

6.3.4 Environmental Conditions ........................... 48

6.3.5 Inputs ...................................... 48

6.3.6 Recycling .................................... 48

1 Introduction

The Ndigo5G is a digitizer and transient recorder designed to sample relatively shorts pulses

in rapid repetition. It produces a stream of output packets, each containing data from a single

trigger event together with a timestamp.

1.1 Features



10 bit dynamic range



up to 5 Gsps sample rate (in 1 channel mode)



up to 4 channels



digital input with TDC that can also be used for gating and triggering



2nd digital input for gating or triggering



PCIe 4x 1.1 with 800 MB/s throughput



multiple boards can be synchronized



extension board with 4 additional digital inputs.

2 Hardware

2.1 Installing the Board

The Ndigo5G board can be installed in any x4 (or higher amount of lanes) PCIe slot. If the slot

electrically supports less than 4 lanes, the board will operate at lowerdata throughput rates.

Please ensure proper cooling of the device. The Ndigo5G has an onboard temperature detec-

tion. If the ADC chip temperature exceeds 90◦C a warning is issued to the device driver. In case

the temperature is higher than 95◦C the ADC is disabled to avoid damage. Using a PCI-slot

cooler is in many cases an appropriate solution to circumvent problems caused by overheating

if the board is used inside a PC. The Ndigo-Crate will provide suﬃcient cooling under normal

operating conditions.

Using a single Ndigo5G, no further connections need to be made. For applications that

require more than 4 ADC channels, several Ndigo boards can be operated in sync. Any board

of the Ndigo product line can be synced to other Ndigo boards, allowing, for instance, for a

combination of high speed ADCs (Ndigo5G) and slower high resolution ADCs (Ndigo250M-14)

or the upcoming Ndigo TDC.

The signals used for board synchronization and inter-board triggering are transferred on a

bus be-tween the boards. Join all C2 connectors (see Figure 2.3 on page 5) on the boards using

a ribbon cable. Both ends of the bus need to be terminated properly. If using a Ndigo Crate,

connectors providing the termination are located on the crate mainboard next to the PCIe slots

to the extreme left and right. For more details, please refer to the Ndigo Crate user guide. In

applications that use only a few Ndigo boards installed directly inside a PC, termination PCBs

available from cronologic can be used.

Ndigo5G’s standard device driver can be used to read out all boards and acquire data. For

more complex scenarios, using the cronoSync-library, which is part of cronoTools, is recom-

mended. The cronoSync library is provided with the Ndigo device driver. Please refer to the

cronoTools user guide for more information.

termination

Figure 2.1: If several Ndigo boards are connected to work in sync , the boards must be connected

using a ribbon cable as bus for synchronization and trigger signals. At both ends of

the cable, proper termination is required.

2.2 Ndigo5G External Inputs and Connectors

2.2.1 Connectors

The inputs of the Ndigo5G are located on the PCI bracket. Figure 2.3 on page 5shows the

location of the 4 analog inputs A to D and the two digital inputs G (GATE) and T (Trigger).

Furthermore, two board interconnection connectors can be found at the top edge of the Ndigo5G,

as displayed in Figure 2.3 on page 5. Connector C1 is used for a board-to-board connection (e. g.

to link a HPTDC8-PCI and a Ndigo5G via a Ndigo Extension board, see chapter 2.3). Connector

C2 is used as a bus interface between multiple Ndigo boards distributing clock, trigger and sync

signals. Proper termination must be placed at both ends of the bus interconnection ribbon

cable.

Figure 2.2: Input connectors of an Ndigo5G located on the PCI bracket.

cronologic GmbH & Co. KG 4 Ndigo5G User Guide

Figure 2.3: Schematics of an Ndigo5G board showing inter-board connectors C1 and C2.

2.2.2 Analog Inputs

TC1-1-I3M+

Lemo 00 connector

analog-offset[i]

EV10AQ190

DAC

Figure 2.4: Input circuit for each of the four analog channels.

The analog inputs of the ADC are single ended LEMO00 coax connectors. The inputs have

a 50Ω impedance and are AC coupled. The inputs are converted to a diﬀerential signal using a

balun.

Analog Oﬀsets

AC coupling removes the common mode voltage from the input signal. Users can move the

common mode voltage to a value of their choice using the analog oﬀset parameter of each

channel before sampling.

This feature is useful for highly asymmetric signals, such as pulses from TOF spectrometers

or LIDAR systems. Without analog oﬀset compensation, the pulses would begin in the middle

of the ADC range, eﬀectively cutting the dynamic range in half (see Figure 2.6). By shifting

the DC baseline to one end of the ADC range, the input range can be used fully, providing the

maximum dynamic range. The analog oﬀset can be set between ±0,25V.

cronologic GmbH & Co. KG 5 Ndigo5G User Guide

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