Casio CTK-500 Manual de usuario
(with price)
CTK-500
ELECTRONIC KEYBOARD
R
CTK-500
- 2 -
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Circuit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Major Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
PCB Views and Major Check Points . . . . . . . . . . . . . . . . . . . . . . . . 8
Schematic Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Troubleshooting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
IC and Transistor Lead Identification . . . . . . . . . . . . . . . . . . . . . 12
Exploded View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
CONTENTS
— 1 —
General
Number of Keys: 61
Polyphonic: 16-note
Preset Tones: 120
Auto-Rhythms: 40
Auto-Accompaniment: CASIO Chord/Fingered
Jukebox Tunes: 40
Chord Memory: Real-Time Recording
Memory Capacity: 128 chords (maximum)
Built-In Speakers: 12 cm dia. 1.1W Input Rating: 2 pcs.
Terminals: Output Jack [Output Impedance: 50 Ω, Output Voltage: 1.4 V (rms)MAX],
AC Adapter Jack (DC 9 V)
Auto Power Off: Approximately 6 minutes after the last operation
Power Source: 2-way AC or DC source
AC: AC adapter
DC: 6 D size dry batteries
Power Consumption: 6.7 W
Dimentions: 110 x 939 x 337 mm (HWD)
(4-5/16 x 36-15/16 x 13-1/4 inches) (HWD)
Weight: 4.5 kg (9.9 lbs) excluding batteries
Electrical
Current Drain with 9V DC:
No Sound Output 125 mA ±30%
Maximum Volume 530 mA ±30%
with keys C4 to D#5 pressed in Clarinet tone,
Volume; Maximum, Rhythm; Samba,
Tempo; Maximum
Output Level (Vrms with 8 Ωload each channel): 107 mV ±30%
with key C4 pressed in Clarinet tone,
Volume; Maximum
Sound Pressure Level: 107 dB ±10 dB
at 10 cm away from the speaker with key G6
in Brass-1 tone
Minimum Operating Voltage: 6.0 V
SPECIFICATIONS
— 2 —
LEDs
LED Driver
IC3
KO0 ~ KO5, KO17
OE
CE
A0 ~ A16
D0 ~ D15
43.45 MHz Clock
Keys and Switches
KO0 ~ KO16
KI1 ~ KI7
CPU
MSM6626-01
LSI1 ROM
MN232000CUQ
LSI2
ROUT
LOUT
Reset IC
S8053ANO
IC4
KO18
(APO)
VCCAVDDVDD
Power Amp.
LA4127
IC2
Output
Power IC
CA5668
IC1
Filter (R)
T5
Filter (L)
T6
Speakers
Main Volume
Control
X1
BLOCK DIAGRAM
— 3 —
CIRCUIT DESCRIPTION
Key and Switch Matrix
KI0 KI1 KI2 KI3 KI4 KI5 KI6 KI7
KO0 C2 C#2 D2 D#2 E2 F2
KO1 F#2 G2 G#2 A2 A#2 B2
KO2 C3 C#3 D3 D#3 E3 F3
KO3 F#3 G3 G#3 A3 A#3 B3
KO4 C4 C#4 D4 D#4 E4 F4
KO5 F#4 G4 G#4 A4 A#4 B4
KO6 C5 C#5 D5 D#5 E5 F5
KO7 F#5 G5 G#5 A5 A#5 B5
KO8 C6 C#6 D6 D#6 E6 F6
KO9 F#6 G6 G#6 A6 A#6 B6
KO10 C7 Tempo
Up Tempo
Down
KO11 Power
Off Normal Fingered CASIO
Chord
KO12 Accomp.
Volume 1
(Min)
Accomp.
Volume 2 Accomp.
Volume 3 Accomp.
Volume 4
Accomp.
Volume 5
(Max)
KO13 Reverb Off Reverb 1 Reverb 2
KO14 Synchro
/ Fill-In Start/Stop Intro/
Ending
Chord
Memory
Record
Chord
Memory
Play
Ad-Lib
Musician Jukebox
Start/Stop Beat
(Jukebox)
KO15 Bank A Bank B Bank C Bank D Bank E Bank F Bank G Bank H
KO16 Number 1 Number 2 Number 3 Number 4 Number 5 Solo
Sound Duo
Sound Ensenble
Sound
— 4 —
F#3 G#3 A#3 C#4 D#4 F#4 G#4 A#4 C#5 D#5 F#5 G#5 A#5
F3 G3 A3 B3 C4 D4 E4 F4 G4 A4 B4 C5 D5 E5 F5 G5 A5 B5 C6
D#3
C2 D2 E2 F2 G2 A2 B2 C3 D3 E3 B6A6G6F6E6D6 C7
C#3A#2G#2
F#2D#2
C#2 A#6
G#6F#6D#6
C#6
CPU (LSI1: MSM6626-01)
The CPU reads sound data from the ROM in accordance with the pressed key and the selected tone; the
CPU can read rhythm data simultaneously when a rhythm pattern is selected. Then it provides the left
and the right channels' waveforms separately, by converting the data into the waveforms with two built-in
DACs. The CPU also controls keys, switches, and LEDs.
The following table shows the pin functions of LSI1.
Pin No. Terminal In/Out Function
1 ~ 10
74 ~ 80 KO0 ~ KO16 Out Using time sharing, the terminals provide key and switch
scan signals, and LED drive signals.
11 KO17 Out Clock output for the LED driver
12 KO18 (APO) Out APO (Auto Power Off) signal output.
13 KO20 Out Not used.
14 ~ 21 KI0 ~ KI7 In Input terminals from the keys and switches
22 -MI In Power ON trigger pulse input.
23 -RESET In CPU reset signal input.
24 REFH In Low level reference voltage input for the built-in DAC
25 AVDD In +5 V source for the built-in DAC
26 ROUT Out Right channel sound signal output
27 LOUT Out Left channel sound signal output
28 AGND In Ground (0 V) source for the built-in DAC
29 REFL In High level reference voltage for the built-in DAC
30, 31 TEST1, TEST2 Not used. Connected to ground.
32 GND In Ground (0 V) source
33, 34 COSI, COSO In/Out 43.45 MHz clock input/output
35 VDD In +5 V DC source. Regardless of the power switch position,
the terminal always receives +5 V DC.
36 -CE Out Chip enable signal output. Low effective.
37 -OE Out Read enable signal output. Low effective.
38 ~ 40 ADR17 ~ ADR19 Out Not used.
41 ~ 57 ADR0 ~ ADR16 Out Address bus for the ROM
58 ~ 73 DIN0 ~ DIN15 In Data bus for the ROM
Nomenclature of Keys
— 5 —
From the CPU
To main volume
FIlter Block
Since the sound signall from the CPU is a stepped waveform, the filter block is added to smooth the
waveform. VDD
1K
AG AG AG
10K 10K 6.2K
C562(H)
C222(H)
C331J
2SC3112B
VDD
CPU
MSM6626-01
LSI1
VDD
ON
OFF
ON
OFF
MI
KO11
KI1
KI0
Power Switch
ON
KO18
APO signal
OFF: 0V
ON: +5 V
Power On/Off Circuit
When the power switch is turned on, a low level differential pulse is provided to terminal MI of the CPU.
Upon receipt of the pulse, the CPU starts the power ON sequence and raises the APO signal to +5 V.
When the switch is off, on receiving the KO11 signal at terminal KI0, the CPU drops the APO signal to
ground level to shut down power.
Initial Reset Circuit
When batteries are set or an AC adapter is connected, the reset IC provides a low pulse to the CPU.
The CPU then initializes its internal circuit.
VDD Battery set
RESET
CPU
MSM6626-01
LSI1
Reset IC
S8053ANO
IC4
— 6 —
Power IC (IC1: CA5668)
The power IC generates three voltages AVDD (+5 V) for the CPU and the reset IC, AVDD (+5 V) for the
analog circuit, and VCC (+9 V) for the power amplifier. VDD (+5 V) is always generated, but AVDD (+5 V)
and VCC (+ 9V) are controlled by the APO signal.
KO0
KO1
KO2
KO3
KO4
KO5
KO17
D3
D5
D2
D6
D1
D4
Q3
Q5
Q2
Q6
Q1
Q4
L0
L1
L2
L3
L4
L5
CPU
MSM6626-01
LSI1
LED Driver
TC74CH174AP
IC3
Chord Memory Play
Solo Sound
Duo Sound
Ensenble Sound
Beat (Jukebox)
Ad-Lib Musician
VDD
CLK
CLR
LED Driving
VDD
AVDD
VCC
APO
VIN
VDIN
GND
CA5668
IC1
+9V
APO VDD AVDD VCC
0 V +5 V 0 V 0 V
+5 V +5 V +5 V +9 V
— 7 —
MAJOR WAVEFORMS
— 8 —
1
23
56
789
10
11 12
13 4
PCB VIEWS AND MAJOR CHECK POINTS
Volume PCB M5505-MA2M
Main PCB M5505-MA1M
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