Avnet Zynq Mini-ITX Manual de usuario

Avnet Zynq Mini-ITX Development Board

ARM PJTAG Interface

Version 1.0

August 2015

1Introduction

This document describes a simple Zynq design that can be used to allow the ARM

DSTREAM debug device to be connected to the Avnet Zynq Mini-ITX development

board.

2Reference Design Requirements

This reference design will require the following software and hardware setups.

2.1 Software

The software requirements for this reference design are:

Xilinx Vivado 2015.2

2.2 Hardware

The hardware setup for this reference design is:

Computer with 4 GB RAM and 1 GB virtual memory (recommended)

Avnet Zynq Mini-ITX Development Board

Power supply Module

ATX power supply

USB A-mini-B cable

ARM DSTREAM Debug Adapter

microSD card

3Reference Design Block Diagram

The following figure shows a high-level block diagram of the reference design. The

reference design is intended to show how to connect the ARM DSTREAM debug adapter

to the Zynq Mini-ITX board via the ARM PJTAG port.

The ARM PJTAG port is NOT connected to the Zynq dedicated PJTAG pins on the Zynq

Mini-ITX board, it is connected to the Zynq PL pins (referred to as EMIO pins). So, prior

to connecting the ARM DSTREAM debug adapter to the Zynq Mini-ITX board, a design

that connects the ARM PJTAG port to the ARM processor via the PL pins must be must

be loaded in to the Zynq device. This reference design implements the connection of the

ARM PJTAG port to the ARM processor via the PL pins. Users can use the steps taken in

this design to include the ARM PJTAG interface in their own design running on the

Avnet Zynq Mini-ITX board.

Figure 1 – Reference Design Block Diagram

4Setting up the Board and the PC

Please perform the following steps to setup the Zynq Mini-ITX board.

1. Install a jumper on JP1 pins 1-2.

2. Install a jumper on JP7 pins 3-4.

3. Install a jumper on JP12 pins 2-3.

4. Connect the USB A-mini-B cable to J7 and the USB port of the PC (USB-UART

connection).

5. If not already installed, install the power module onto the Mini-ITX board via J8,

J9, and J10 connectors.

6. Connect the ATX power supply to P2 connector.

7. Connect the ARM DSTREAM adapter to the Mini-ITX PJTAG header (J11).

8. Start a Tera Term session and set the serial port parameters to 115200 baud rate, 8

bits, 1 stop bit, no parity and no flow control (please refer to the Setting up the

Host PC section at the end of this document for installing the software driver for

the USB-UART port and setting up the UART).

5Reference Design Vivado IPI Project

Start the Vivado tool via Start > All Programs > Xilinx Design Tools > Vivado

2015.2 > Vivado 2015.2

Open the Vivado IPI zynq_mini_itx_pjtag_design project (the archived project

file is located in the root directory of the reference design folder). Click on the

Open Block Design (under the IP Integrator) and select zynq_design_1.bd file.

The Vivado IPI GUI should look as shown in the following figure.

Note: If you are using a Windows PC and encounter Windows 260 character path limit

issue when trying to rebuild the hardware platform in Vivado (the hardware platform is

already built for you), please refer to the Xilinx Answer Record #52787 to resolve the

issue. http://www.xilinx.com/support/answers/52787.htm

In addition to the above Answer Record, you could set your “Temp” environment

variable to a short path. To do this, create a folder on your C drive and call it MyTemp.

Set the “Temp” environment variable to C:\MyTemp.

Double-click on the ZYNQ device in the Vivado Block Design to open the PS

Configurator. Click on the MIO Configuration and noticed that the PJTAG box

is checked and PJTAG interface I/Os are mapped to the EMIO pins (I/Os pins in

the Zynq PL). Click Cancel to continue.

Double-click on the system.xdc file to open it.

As shown, the PJTAG interface I/O pins are mapped to the Zynq PL I/O pins.

6Reference Design Files

Unzip the reference design to your hard drive. The reference design zip file

contains the following folder and zip file:

ozynq_mini_itx_pjtag_design.zip

oready_to_download

The zynq_mini_itx_pjtag_design.zip file contains the archived of the Vivado

2013.4 design that shows how to connect the ARM PJTAG port to the Zynq

Programmable Logic (PL) EMIO pins. The ready_to_download folder contains

files that are needed to boot the Zynq Mini-ITX board and enable the ARM

PJTAG connections.

The ready_to_download folder contains the following files:

oZynq Mini-ITX board FSBL ELF file (generated by exporting the

reference design Vivado project to SDK)

oPL bitstream to connect the PJTAG signals to the PL EMIO pins

(bitstream is generated via the Vivado project)

oU-Boot ELF file (this is a pre-build file for the Zynq Mini-ITX board)

omicroSD card boot.bin image used to boot the Zynq processor (you can

re-create this image using the above 3 files in SDK, if needed)

7Running the Reference Design on the Zynq Mini-ITX Board

Copy the content of your microSD card to your hard drive so that you can restore

the microSD card content that was shipped with your Zynq Mini-ITX board.

Delete the content of the microSD card.

Copy the ready_to_download/boot.bin file to the root directory of the microSD

card.

Set the Zynq Mini-ITX board PS mode switch (SW7) for SD card boot with

“Independent JTAG”. This means the SW7 positions 1-5 must be set to 10110.

Insert the microSD card into the microSD card socket located on the Zynq Mini-

ITX board (J4).

Power up the board (SW12) and let the microSD card configure the PL (blue

DONE LED next to the PCIe slot will be illuminated).

Once PL is configured, U-Boot will begin to run in Tera Term terminal (at this

time PS-to-PL level shifters are enabled). Hit the return key to stop the auto-boot.

You should see the following in the Tera Term terminal.

The ARM PJTAG interface is now ready to be used by the ARM DSTREAM.

8Setting up the Host PC

This section describes how to install the USB drivers on the host PC for the USB-

UART connection to the Zynq Mini-ITX board.

8.1 Install the USB UART Drivers

Download and install the Silicon Laboratories CP210x VCP drivers on the host

computer. The drivers are available for download at

http://www.silabs.com/products/mcu/Pages/USBtoUARTBridgeVCPDrivers.aspx

8.2 Configure the Host Computer COM Port

The Reference design uses a terminal program to communicate between the host

computer and the Mini-ITX board. To configure the host computer COM port for this

purpose:

1. Connect the Mini-ITX board to the host computer via the J7 USB-UART port

and power up the board.

2. Open the host computer Device Manage as shown in the following figure. In

the Windows task bar, click Start, click Control Panel, and then click Device

Manager.

3. Open UART properties. Expand Ports (COM & LPT), right-click Silicon Labs

CP210x USB to UART Bridge, and then click Properties.

4. In the properties window, select the Port Settings tab, verify the settings match

the values shown in the following figure. Click on the Advanced button to

continue.

115200

None

5. Select an unused COM Port Number and then click OK. The following figure

shows COM1 as the selected COM port number.

6. Click OK in the properties window, close the Device Manager and the Control

Panel.

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