ASAHI AKD55X4-B Manual de usuario

[AKD55X4-B]

<KM119202> 2015/09

GENERAL DESCRIPTION

The AKD55X4-B is an evaluation board for AK55X4/X2, which is 32bit, 8k – 768kHz, 4ch/2ch ADC.

4ch ADC (AK55X4) : AK5534, AK5554, AK5574 2ch ADC (AK55X2) : AK5552, AK5572

The AKD55X4-B is includes the analog input circuit and also has a digital interface transmitter .

Further, the AKD55X4-B can achieve the interface with digital audio systems via BNC-connector.

Ordering guide

AKD55X4-B -- Evaluation board for AK55X4/X2

FUNCTION

DIT with BNC or Optical digital output.

ADC 4ch/2ch input is possible.

BNC connector for an external clock input.

AK4118A

(DIT)

AIN1

AIN2

Clock

Generator

+VOP

Input

Buffer

AK55X4

AK55X2

-VOP

TVDD

Regulators

5V/3.3V

+15V

-15V

AVDD

3.3V

BNC_TX

(OUT)

DSP Data

10pin Header

AIN3

AIN4

Input

Buffer

ｷｬﾉﾝｺﾈｸﾀ

(IN)

OPT_TX

(OUT)

1.8V

VDD18

Figure 1. AKD55X4-B Block Diagram

* Circuit diagram and PCB layout are attached at the end of this manual.

AK55X4/X2 Evaluation Board Rev.2

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[AKD55X4-B]

<KM119202> 2015/09

Evaluation Board Diagram

Board Diagram

J801 J802 J800

SW604

SW600

J200

J202 J203

J201

SW603

SW601

PORT500

T1 T2

J805 J804

J806 J807 J808

J809

J300

J302 J303

J301

SW602

J400

PORT400

PORT602

PORT601

PORT600

PORT610

J600

SW400

AKD55X4-B

AK55X4/X2

-15V VSS +15V VBIAS AVDD VCC TVDD VDD18 D3.3V

Figure 2. AKD55X4-B Board Diagram

Description

(1) U1 ( AK55X4/AK55X2 )

32bit,8k - 768kHz,4ch/2ch A/D Converter.

(2) J200,J201,J300,J301 ( Analog data )

Cannon connector : Differential Analog Input

(3) J202,J203,J302,J303 ( Analog data )

BNC Connector : Single-ended Analog Input.

(4) J400 / PORT400 ( Digital data )

BNC Connector / Optical Connector: Digital Output.

(5) J800, J801, J802,J804,J805,J806,J807,J808,J809 ( Power supply )

Power Supply Connector.

(6) PORT600,PORT601 ( pin header )

Pin header for evaluation (MCLK, BICK, LRCK, SDTO1, SDTO2, TDMIN).

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[AKD55X4-B]

<KM119202> 2015/09

(7) PORT602 ( pin header )

Pin header for evaluation (DCLK, DSDOL1/R1, DSDOL2/R2).

(8) U4 ( AK4118A )

AK4118A has DIT. Transports output data from AK55X4/X2.

(9) SW600 ( Toggle switch )

Toggle type-switch PDN for AK55X4/X2.

“H” : PDN = High

“L” : PDN = Low

(10) SW601 ( Toggle switch )

Toggle type-switch PDN for AK4118A.

“H” : PDN = High

“L” : PDN = Low

(11) SW602,SW603,SW604 ( Dip switch)

DIP type-switch for AK55X4/X2.

“H” : Digital signal = High

“L” : Digital Signal = Low

(12) SW400 ( Dip switch (Dual In-line Package switch)

DIP type-switch for AK4118A.

“H” : Digital signal = High

“L” : Digital Signal = Low

(13) J600 ( MCLK external input )

BNC Connector : External Clock Input (MCLK).

(14) T1, T2, T3, T4, T5

Regulator for AK55X4/X2, AK4118A, Logic Circuit.

T1 : Regulated AVDD, VBIAS (5.0V/3.3V) from +15V.

T2 : Regulated VCC1, VCC2 (5.0V) from +15V.

T3 : Regulated TVDD (3.3V) from +5V.

T4 : Regulated TVDD, VDD18 (1.8V) from +5V

T5 : Regulated D33V (3.3V) from +5V.

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[AKD55X4-B]

<KM119202> 2015/09

Evaluation Board Manual

Operation sequence

[1] Power supply line settings

[2] Jumped pins settings

[3] DIP switches settings

[4] Toggle switches settings

[5] Register control (Serial control)

[6] Evaluation modes

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[1] Power supply line settings

(1-1) Power supply settings : Used the regulator (T1,T2,T3,T4,T5) <Default>

Set up the power supplied lines :

* Each supply line should be distributed from the power supply unit.

Name Color Setting (Typ) Function Comments Default Settings

J800 +15V Green +15V Regulator and Op-amp

power supply

Should always be connected +15V

J801 -15V Blue -15V Regulator and Op-amp

power supply

Should always be connected -15V

J804 AVDD Red +5.0V / 3.3V AK55X4/X2 AVDD 5.0V/3.3V regulator is used,

R807=short by default.

When jack is used,

R808=short.

REG :

(R807 = short)

J805 VBIAS Red +5.0V / 3.3V Referential Voltage

source for Op-amp

5.0V/3.3V regulator is used,

R809=short by default.

When jack is used,

R810=short.

REG :

(R809 = short)

J809 VCC Red +5.0V 3.3V Regulator power

supply

5.0V regulator is used,

R811=short by default.

When jack is used,

R812=short.

REG :

(R811 = short)

J806 TVDD Orange +1.8 / +3.3V/ AK55X4/X2 TVDD,

Logic IC power supply

3.3V regulator is used,

JP800=3.3V and JP801=REG

by default.

When 1.8V regulator is used,

JP800=1.8V and JP801=REG.

When jack is used,

JP801=JACK short.

REG (3.3V) :

(JP800=3.3V and

JP801=REG)

J807 VDD18 Orange +1.8V AK55X4/X2 VDD18 LDO of AK55X4/X2 is used,

JP802=open by default.

When 1.8V regulator is used,

JP802=REG.

When jack is used,

JP802=JACK.

Open :

(JP802=open)

J808 D3.3V Orange +3.3V AK4118A 3.3V VDD,

Logic IC power supply

3.3V regulator is used,

JP803=REG by default.

When jack is used,

JP803=JACK.

REG :

(JP803=REG)

J802 VSS Black 0V Ground Should always be connected 0V

Table 1-1. Power supply line setting ( default : used the regulator )

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(1-2) About jumper for power supply :

The roles of the jumper or the short resistance for each power supply supplied from the regulator are as follows.

Connection of the jumper for power supply :

Name Function Comments Default Settings

R807

R808

AVDD1 Select regulator power supply

or jack for AVDD1

AVDD for AK55X4/X2:

R1007=short : 5.0V/3.3V regulator is used. (default)

R1008=short : Jack is used.

REG :

R807=short

R808=open

R809

R810

VBIAS Select regulator power supply

or jack for VBIAS

VBIAS for Op-amp Referential Voltage source:

R809=short : 5.0V/3.3V regulator is used. (default)

R810=short : Jack is used.

REG :

R809=short

R810=open

R811

R812

VCC1,

VCC2

Select regulator power supply

or jack for 5.0V Regulator

power supply

VCC1, VCC2 for 5.0V Regulator power supply:

R811=short : 5.0V regulator is used. (default)

R812=short : Jack is used.

REG :

R811=short

R812=open

JP800 TVDD-VSEL Select regulator power supply

3.3V or 1.8V for TVDD

TVDD for AK55X4/X2 and Logic IC:

JP800=3.3V : 3.3V regulator is used. (default)

JP800=1.8V : 1.8V regulator is used.

3.3V :

JP800=3.3V

JP801 TVDD-SEL Select regulator power supply

or jack for TVDD

TVDD for AK55X4/X2 and Logic IC:

JP801=REG : Regulator is used. (default)

JP801=JACK: Jack is used.

REG :

JP801=REG

JP802 VDD18-SEL Select External power supply or

LDO power supply of AK55XX

for VDD18

VDD18 selector for AK55X4/X2:

JP802=REG : External Power supply of 1.8V regulator is

used.

JP802=JACK : External Power supply of Jack is used.

JP802=open : LDO of AK55X4/X2 is used. (default)

LDO of AK55XX :

JP802=open

JP803 D33V-SEL Select regulator power supply

or jack for D33V

D33V for AK4118A and Logic IC:

JP1003=REG : 3.3V regulator is used. (default)

JP1003=JACK : Jack is used.

REG :

JP803=REG

Table 1-2. Jumper for power supply

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[2] Jumped pins settings

No Names Default Functions

1 JP400 TXDATA-SEL COAX Select COAX / Optical Connector for TX data of AK4118A.

COAX: COAX for TX data of AK4118A. (default)

OPT: Optical for TX data of AK4118A.

2 PORT605 BICK-SEL DIT Select input / output to AK55X4/X2 (U1) BICK

DIT: BICK-AK4118A-T (default)

PORT: Pin Header PORT600-BICK

GND: Connected to VSS

Open: No signal

3 PORT606 LRCK-SEL DIT Select input / output to AK55X4/X2 (U1) LRCK

DIT: LRCK-AK4118A-T (default)

PORT: Pin Header PORT600-LRCK

GND: Connected to VSS

Open: No signal

4 PORT607 BICK-PHASE THR Select polarity (non-inverted output / inverted output) of

BICK_SEL inputs / outputs.

THR: Non-inverted output. (default)

INV: Inverted output.

5 PORT608 SDTO_SEL SDTO1 Select input to DIT:AK4118A (U4) DAUX

SDTO1: AK55X4/X2-SDTO1 is used. (default)

SDTO2: AK55X4/X2-SDTO2 is used.

open: No signal for DAUX-AK4118A-T

6 PORT609 TDMI-SEL Open Select connect to AK55X4/X2 (U1) TDMI

Open: No signal for TDMIN (default)

Short: Pin Header PORT601-TDMIN

7 PORT610 MCKI-SEL DIT Select input to AK55X4/X2 (U1) MCLK

DIT: MCLK-AK4118A-T (default)

PORT: Pin Header PORT600-MCLK

EXT: External MCLK (JACK:J600 EXT) input.

GND: Connected to VSS

8 JP600 EXT Open Open: No input (default)

Short: External MCLK (JACK:J600 EXT) input.

9 JP700 PS-SEL1 SDA/CDTI Select input / output to AK55X4/X2 (U1) CKS0/SDA/CDTI

SDA/CDTI:

SDA/CDTI signal input / output to AK55X4/X2. (default)

CKS0:

CKS0 signal of SW803 input to AK55X4/X2.

10 JP701 PS-SEL2 CAD0-I2C/CSN Select input to AK55XX (U1) CKS1/CAD0-I2C/CSN

CAD0-I2C/CSN:

CAD0-I2C/CSN signal input to AK55XX. (default)

CKS1:

CKS1 signal of SW803 input to AK55XX.

11 JP702 PS-SEL3 CAD0-I2C Select input to JP701 CAD0-I2C/CSN

CAD0-I2C:

CAD0-I2C signal of SW602 input to JP701. (default)

CSN:

CSN signal of SW602 input to JP701.

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[AKD55X4-B]

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12 JP703 PS-SEL4 SCL/CCLK Select input to AK55X4/X2 (U1) CKS2/SCL/CCLK

SCL/CCLK:

SCL/CCLK signal input to AK55X4/X2. (default)

CKS2:

CKS2 signal of SW603 input to AK55X4/X2.

13 JP704 PS-SEL5 CAD1 Select input to AK55X4/X2 (U1) CKS3/CAD1

CAD1: CAD1 signal input to AK55X4/X2. (default)

CKS3: CKS3 signal of SW603 input to AK55X4/X2.

14 JP705 PS-SEL6 PS Select input to AK55X4/X2 (U1) PS/CAD0-SPI

PS:

PS signal input to AK55X4/X2. (default)

CAD0-SPI:

CAD0-SPI signal of SW602 input to AK55X4/X2.

15 JP800 TVDD-VSEL 3.3V Select power supply voltage of TVDD

3.3V: Regulator T3 (+5V => 3.3V) (default)

1.8V: Regulator T4 (+5V => 1.8V)

16 JP801 TVDD-SEL TVDD Select power supply to TVDD

REG: Regulator T3/T4 (default)

JACK: Power supply jack J806 “TVDD”

17 JP802 VDD18-SEL REG Select power supply to VDD18

REG: Regulator T4 (default)

JACK: Power supply jack J807 “VDD18”

18 JP803 D33V-SEL REG Select power supply to D33V

REG: Regulator T5 (+5V => 3.3V) (default)

JACK: Power supply jack J808 “D3.3V”

Table 2. Main board Jumper pin setting

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[3] DIP switches settings

(3-1). Setting for SW400 (Sets AK4118A (U4) audio format and master clock setting)

No. Switch Name Function default

1 DIF2 Set-up of DIF0 pin. H

2 DIF1 Set-up of DIF1 pin. L

3 DIF0 Set-up of DIF2 pin. H

4 OCKS1 Set-up of OCKS1 pin. H

5 OCKS0 Set-up of OCKS0 pin. L

Table 3-1. SW400 Setting (AK4118A)

Mode

DIF2 pin

SW400_1

DIF1 pin

SW400_2

DIF0 pin

SW400_3 DAUX SDTO LRCK BICK

DIF2 bit DIF1 bit DIF0 bit I/O I/O

0 0 0 0 24bit, Left

justified

16bit, Right

justified H/L O 64fs O

1 0 0 1 24bit, Left

justified

18bit, Right

justified H/L O 64fs O

2 0 1 0 24bit, Left

justified

20bit, Right

justified H/L O 64fs O

3 0 1 1 24bit, Left

justified

24bit, Right

justified H/L O 64fs O

4 1 0 0 24bit, Left

justified

24bit, Left

justified H/L O 64fs O

5 1 0 1 24bit, I2S 24bit, I2S L/H O 64fs O default

6 1 1 0 24bit, Left

justified

24bit, Left

justified H/L I 64-128fs I

7 1 1 1 24bit, I

S 24bit, I

S L/H I 64-128fs I

Table 3-2. Audio format (AK4118A)

OCKS1 pin

SW400_4

OCKS0 pin

SW400_5 (X’tal) MCKO1 MCKO2 fs (max)

OCKS1 bit OCKS0 bit

0 0 256fs 256fs 256fs 96 kHz

0 1 256fs 256fs 128fs 96 kHz

1 0 512fs 512fs 256fs 48 kHz default

1 1 128fs 128fs 64fs 192 kHz

Table 3-3. Master Clock Frequency Select (AK4118A)

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(3-2). Setting for SW802 (Sets AK55X4/X2 (U1) )

No. Switch Name Function default

1 TEST TEST Enable. L

2 PW0 ADC Power Management and Monaural / Stereo select. H

3 PW1 ADC Power Management and Monaural / Stereo select. H

4 PW2 ADC Power Management and Monaural / Stereo select. H

5 MSN

Master/Slave select.

L: Slave Mode

H: Master Mode

6 CAD0-SPI Chip Address0 Pin in 3-wire serial control mode.

(I2C pin =”L”)

7 CAD0-I2C Chip Address0 Pin in I2C bus serial control mode.

(I2C pin =”H”, PS pin =”L”)

8 CAD1

Chip Address1 Pin in I2C bus or 3-wire serial control mode.

(3-wire : I2C pin =”L”)

(I2C bus : I2C =”H”, PS pin ”L”)

Table 3-4. SW602 Setting

(3-3). Setting for SW603 (Sets AK55X4/X2 (U1) )

No. Switch Name Function default

1 CKS0 Clock Mode Setting #0 L

2 CKS1 Clock Mode Setting #1 H

3 CKS2 Clock Mode Setting #2 H

4 CKS3 Clock Mode Setting #3 L

5 DIF0/DSDSEL0

DIF0 : Audio Data Format select in PCM Mode

L: MSB justified

H: I2S

DSDSEL0 : DSD Sampling Rate Control in DSD Mode

6 DIF1/DSDSEL1

DIF1 : Audio Data Format select in PCM Mode

L: 24-bit Mode

H: 32-bit Mode

DSDSEL1 : DSD Sampling Rate Control in DSD Mode

7 SLOW/DCKB SLOW : Slow Roll-OFF Digital Filter select in PCM Mode

DCLKB : Polarity of DCLK in DSD Mode

8 SD/PMOD SD : Short Delay Digital Filter select in PCM Mode

PMOD : DSD Phase Modulation Mode select in DSD Mode

Table 3-5. SW603 Setting

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