Asahi KASEI AKD5538-B Manual de usuario

[AKD5538-B]

<KM131000> 2018/10

GENERAL DESCRIPTION

The AKD5538-B is an evaluation board for AK5538VN, which is 32bit, 8k –768kHz, 8ch ADC.

The AKD5538-B is includes the analog input circuit and also has a digital interface transmitter .

Further, the AKD5538-B can achieve the interface with digital audio systems via BNC-Connector.

Ordering guide

AKD5538-B -- Evaluation board for AK5538VN

FUNCTION

•DIT with BNC or Optical digital output.

•ADC 8ch input is possible.

•BNC Connector for an external clock input.

AK4118A

(DIT)

AIN1

AIN2

Clock

Generator

+VOP

Input

Buffer

AK5538

-VOP

TVDD

Regulators

+3.3V

+15V

-15V

AVDD

+3.3V

BNC_TX

(OUT)

DSP Data

10pin Header

AIN3

AIN4

Input

Buffer

AIN5

AIN6

Input

Buffer

AIN7

AIN8

Input

Buffer

INPUT

OPT_TX

(OUT)

+1.8V

VDD18

Figure 1. AKD5538-B Block Diagram

* Circuit diagram and PCB layout are attached at the end of this manual.

AKD5538-B

AK5538 Evaluation Board Rev.0

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[AKD5538-B]

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Evaluation Board Diagram

Board Diagram

J1001

J1002

J1000

SW803

SW800

J300

J301

SW804

SW801

PORT801

PORT700

T1001

T1002

J1005

J1004

T1003

J1006

J1007

J1008

J1003

J1009

J201

J200

J400

J401

J500

J501

T1004

T1005

SW802

J600

PORT600

PORT803

PORT802

PORT800

J800

SW600

U100

AKD5538-B

AK5538

Figure 2. AKD5538-B Board Diagram

*AKD5538-B Evaluation Board

Description

(1) U100 ( AK5538 )

32bit,8k - 768kHz,8ch A/D Converter.

(2) J200,J201,J300,J301,J400,J401,J500,J501 ( Analog data )

Cannon Connector : Differential Analog Input

(3) J600 / PORT600 ( Digital data )

BNC Connector / Optical Connector: Digital Output.

(4) J1000, J1001, J1002,J1003,J1004,J1005,J1006,J1007,J1008,J1009 ( Power supply )

Power Supply Connector.

(5) PORT800,PORT801 ( pin header )

Pin header for evaluation (MCLK, BICK, LRCK, SDTO1, SDTO2, SDTO3, SDTO4, TDMIN).

(6) PORT802,PORT803 ( pin header )

Pin header for evaluation (DCLK, DSDOL1/R1, DSDOL2/R2, DSDOL3/R3, DSDOL4/R4).

(7) U200 ( AK4118A )

AK4118A has DIT. Transports output data from AK5538.

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(8) SW800 ( Toggle switch )

Toggle type-switch PDN for AK5538.

“H” : PDN = High

“L” : PDN = Low

(9) SW801 ( Toggle switch )

Toggle type-switch PDN for AK4118A.

“H” : PDN = High

“L” : PDN = Low

(10)SW802,SW803,SW804 ( Dip switch)

DIP type-switch for AK5538.

“H” : Digital signal = High

“L” : Digital Signal = Low

(11)SW600 ( Dip switch (Dual In-line Package switch)

DIP type-switch for AK4118A.

“H” : Digital signal = High

“L” : Digital Signal = Low

(12)J800 ( MCLK external input )

BNC Connector : External Clock Input (MCLK).

(13)T1001, T1002, T1003, T1004, T1005

Regulator for AK5538, AK4118A, Logic Circuit.

T1001 : Regulated AVDD, VBIAS (+3.3V) from +15V.

T1002 : Regulated VCC1, VCC2 (+5.0V) from +15V.

T1003 : Regulated TVDD (+3.3V) from +5V.

T1004 : Regulated TVDD, VDD18 (+1.8V) from +5V

T1005 : Regulated D33V (+3.3V) from +5V.

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Evaluation Board Manual

Operation sequence

[1] Power supply line settings

[2] Jumped pins settings

[3] DIP switches settings

[4] Toggle switches settings

[5] Register control (Serial control)

[6] Evaluation modes

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[1] Power supply line settings

(1-1) Power supply settings : Used the regulator (T1001,T1002,T1003,T1004,T1005) <Default>

Set up the power supplied lines :

* Each supply line should be distributed from the power supply unit.

Name

Color

Setting (Typ)

Function

Comments

Default Settings

J1000

+15V

Green

+15V

Regulator and Op-amp

power supply

Should always be connected

+15V

J1001

-15V

Blue

-15V

Regulator and Op-amp

power supply

Should always be connected

-15V

J1004

AVDD

Red

+3.3V

AK5538 AVDD

+3.3V regulator is used,

R1007=short by default.

When jack is used,

R1008=short.

REG :

(R1007 = short)

J1005

VBIAS

Red

+3.3V

Referential Voltage

source for Op-amp

+3.3V regulator is used,

R1009=short by default.

When jack is used,

R1010=short.

REG :

(R1009 = short)

J1009

VCC

Red

+5.0V

+5.0V Regulator power

supply

+5.0V regulator is used,

R1011=short by default.

When jack is used,

R1012=short.

REG :

(R1011 = short)

J1006

TVDD

Orange

+1.8V / +3.3V

AK5538 TVDD,

Logic IC power supply

+3.3V regulator is used,

JP1000=3.3V and

JP1001=REG by default.

When +1.8V regulator is

used, JP1000=1.8V and

JP1001=REG.

When jack is used,

JP1012=JACK short.

REG (+3.3V) :

(JP1000=3.3V and

JP1001=REG)

J1007

VDD18

Orange

+1.8V

AK5538 VDD18

LDO of AK5538 is used,

JP1002=open by default.

When +1.8V regulator is

used, JP1002=REG.

When jack is used,

JP1002=JACK.

Open :

(JP1002=open)

J1008

D3.3V

Orange

+3.3V

AK4118A +3.3V VDD,

Logic IC power supply

+3.3V regulator is used,

JP1003=REG by default.

When jack is used,

JP1003=JACK.

REG :

(JP1003=REG)

J1002

AVSS

Black

Analog ground

Should always be connected

J1003

DVSS

Black

Digital ground

Should always be connected

Table 1-1. Power supply line setting ( default : used the regulator )

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(1-2) About jumper for power supply :

The roles of the jumper or the short resistance for each power supply supplied from the regulator are as follows.

Connection of the jumper for power supply :

Name

Function

Comments

Default Settings

R1007

R1008

AVDD1

Select regulator power supply

or jack for AVDD1

AVDD for AK5538:

R1007=short : +3.3V regulator is used. (default)

R1008=short : Jack is used.

REG :

R1007=short

R1008=open

R1009

R1010

VBIAS

Select regulator power supply

or jack for VBIAS

VBIAS for Op-amp Referential Voltage source:

R1009=short : +3.3V regulator is used. (default)

R1010=short : Jack is used.

REG :

R1009=short

R1010=open

R1011

R1012

VCC1,

VCC2

Select regulator power supply

or jack for +5.0V Regulator

power supply

VCC1, VCC2 for +5.0V Regulator power supply:

R1011=short : +5.0V regulator is used. (default)

R1012=short : Jack is used.

REG :

R1011=short

R1012=open

JP1000

TVDD-VSEL

Select regulator power supply

+3.3V or +1.8V for TVDD

TVDD for AK5538 and Logic IC:

JP1000=3.3V : +3.3V regulator is used. (default)

JP1000=1.8V : +1.8V regulator is used.

3.3V :

JP1000=3.3V

JP1001

TVDD-SEL

Select regulator power supply

or jack for TVDD

TVDD for AK5538 and Logic IC:

JP1001=REG : Regulator is used. (default)

JP1001=JACK: Jack is used.

REG :

JP1001=REG

JP1002

VDD18-SEL

Select External power supply or

LDO power supply of AK5538

for VDD18

VDD18 selector for AK5538:

JP1002=REG : External Power supply of +1.8V regulator

is used.

JP1002=JACK : External Power supply of Jack is used.

JP1002=open : LDO of AK5538 is used. (default)

LDO of AK5538 :

JP1002=open

JP1003

D33V-SEL

Select regulator power supply

or jack for D33V

D33V for AK4118A and Logic IC:

JP1003=REG : +3.3V regulator is used. (default)

JP1003=JACK : Jack is used.

REG :

JP1003=REG

JP1004

VSS-SEL

Select connection / separation

between analog ground and

digital ground.

Analog ground / digital ground short or open:

JP1004=open: Separate analog ground AVSS from digital

ground DVSS.

JP1004=short: Connect analog ground AVSS to digital

ground DVSS. (default)

Short :

JP1004=short

Table 1-2. Jumper for power supply

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[2] Jumped pins settings

Names

Default

Functions

JP600

TXDATA-SEL

COAX

Select COAX / Optical Connector for TX data of AK4118A.

COAX: COAX for TX data of AK4118A. (default)

OPT: Optical for TX data of AK4118A.

JP801

BICK-SEL

DIT

Select input / output to AK5538 (U100) BICK

DIT: BICK-AK4118A-T (default)

PORT: Pin Header PORT800-BICK

GND: Connected to DVSS

Open: No signal

JP802

LRCK-SEL

DIT

Select input / output to AK5538 (U100) LRCK

DIT: LRCK-AK4118A-T (default)

PORT: Pin Header PORT800-LRCK

GND: Connected to DVSS

Open: No signal

JP807

(PORT807)

BICK-PHASE

THR

Select polarity (non-inverted output / inverted output) of

BICK-SEL inputs / outputs.

THR: Non-inverted output. (default)

INV: Inverted output.

JP803

SDTO-SEL

SDTO1

Select input to DIT:AK4118A (U600) DAUX

SDTO1: AK5538-SDTO1 is used. (default)

SDTO2: AK5538-SDTO2 is used.

SDTO3: AK5538-SDTO3 is used.

SDTO4: AK5538-SDTO4 is used.

open: No signal for DAUX-AK4118A-T

JP804

TDMI-SEL

Open

Select connect to AK5538 (U100) TDMI

Open: No signal for TDMIN (default)

Short: Pin Header PORT801-TDMIN

JP800

MCKI-SEL

DIT

Select input to AK5538 (U100) MCLK

DIT: MCLK-AK4118A-T (default)

PORT: Pin Header PORT800-MCLK

EXT: External MCLK (JACK:J800 EXT) input.

GND: Connected to DVSS

JP810

EXT-T

Open

Open: No input (default)

Short: External MCLK (JACK:J800 EXT) input.

JP1000

TVDD-VSEL

3.3V

Select power supply voltage of TVDD

3.3V: Regulator T1003 (+5V => +3.3V) (default)

1.8V: Regulator T1004 (+5V => +1.8V)

JP1001

TVDD-SEL

TVDD

Select power supply to TVDD

REG: Regulator T1003/T1004 (default)

JACK: Power supply jack J1006 “TVDD”

JP1002

VDD18-SEL

REG

Select power supply to VDD18

REG: Regulator T1004 (default)

JACK: Power supply jack J1007 “VDD18”

JP1003

D33V-SEL

REG

Select power supply to D33V

REG: Regulator T1005 (+5V => +3.3V) (default)

JACK: Power supply jack J1008 “D3.3V”

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JP1004

VSS-SEL

Short

Select connection / separation between analog ground AVSS

and digital ground DVSS.

Open:

Separate analog ground from digital ground

Short:

Connect analog ground to digital ground (default)

Table 2. Main board Jumper pin setting

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[3] DIP switches settings

(3-1). Setting for SW600 (Sets AK4118A (U600) audio format and master clock setting)

No.

Switch Name

Function

default

DIF2

Set-up of DIF0 pin.

DIF1

Set-up of DIF1 pin.

DIF0

Set-up of DIF2 pin.

OCKS1

Set-up of OCKS1 pin.

OCKS0

Set-up of OCKS0 pin.

Table 3-1. SW600 Setting (AK4118A)

Mode

DIF2 pin

SW600-1

DIF1 pin

SW600-2

DIF0 pin

SW600-3

DAUX

LRCK

BICK

24bit, Left

justified

H/L

64fs

24bit, Left

justified

H/L

64fs

24bit, Left

justified

H/L

64fs

24bit, Left

justified

H/L

64fs

24bit, Left

justified

H/L

64fs

24bit, I2S

L/H

64fs

default

24bit, Left

justified

H/L

64-128fs

24bit, I2S

L/H

64-128fs

Table 3-2. Audio format (AK4118A)

OCKS1 pin

SW600-4

OCKS0 pin

SW600-5

(X’tal)

MCKO1

fs (max)

256fs

96 kHz

256fs

96 kHz

512fs

48 kHz

default

128fs

192 kHz

Table 3-3. Master Clock Frequency Select (AK4118A)

(3-2). Setting for SW802 (Sets AK5538 (U100) )

No.

Switch Name

Function

default

TEST

TEST Enable.

PW0

ADC Power Management and Monaural / Stereo select.

PW1

ADC Power Management and Monaural / Stereo select.

PW2

ADC Power Management and Monaural / Stereo select.

MSN

Master/Slave select.

L: Slave Mode

H: Master Mode

Table 3-4. SW802 Setting

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(3-3). Setting for SW803 (Sets AK5538 (U100) )

No.

Switch Name

Function

default

LDOE

LDO Enable

L: LDO Disable

H: LDO Enable

ODP

Output Data Placement Select.

HPFE/DCKS

HPFE : High Pass Filter Enable

L: HPF Disable

H: HPF Enable

DCKS : Master Clock Frequency select at DSD Mode (DSD only)

L: 512fs

H: 768fs

I2C

Control mode select

L: 3-wire serial control mode

H: I2C Bus serial control mode

TDM0

TDM Interface Format select #0

TDM1

TDM Interface Format select #1

DIF1/DSDSEL1

DIF1 : Audio Data Format select in PCM Mode

L: 24-bit Mode

H: 32-bit Mode

DSDSEL1 : DSD Sampling Rate Control in DSD Mode

DIF0/DSDSEL0

DIF0 : Audio Data Format select in PCM Mode

L: MSB justified

H: I2S

DSDSEL0 : DSD Sampling Rate Control in DSD Mode

DSD Mode Enable

L: PCM Mode

H: DSD Mode

PSN

Control mode select (I2C pin =”H”)

L: I2C Bus serial control mode

H: Parallel control mode

Table 3-5. SW803 Setting

- 10-

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