Analog Devices EZ-KIT Lite ADSP-BF506F Guía de aplicación

ADSP-BF50x Blackfin®Processor

Hardware Reference

Revision 1.2, February 2013

Part Number

82-100101-01

Analog Devices, Inc.

One Technology Way

Norwood, Mass. 02062-9106

ment may not be reproduced in any form without prior, express written

consent from Analog Devices, Inc.

Printed in the USA.

Disclaimer

Analog Devices, Inc. reserves the right to change this product without

prior notice. Information furnished by Analog Devices is believed to be

accurate and reliable. However, no responsibility is assumed by Analog

Devices for its use; nor for any infringement of patents or other rights of

third parties which may result from its use. No license is granted by impli-

cation or otherwise under the patent rights of Analog Devices, Inc.

Trademark and Service Mark Notice

The Analog Devices logo, Blackfin, CrossCore, EngineerZone, EZ-KIT

Lite, and VisualDSP++ are registered trademarks of Analog Devices, Inc.

All other brand and product names are trademarks or service marks of

their respective owners.

ADSP-BF50x Blackfin Processor Hardware Reference iii

CONTENTS

PREFACE

Purpose of This Manual .................................................................. li

Intended Audience .......................................................................... li

Manual Contents ........................................................................... lii

What’s New in This Manual ........................................................... lv

Technical Support .......................................................................... lvi

Supported Processors .................................................................. lviiii

Product Information .................................................................. lviiii

Analog Devices Web Site ...................................................... lviiii

EngineerZone .......................................................................... lix

Notation Conventions .................................................................... lx

INTRODUCTION

General Description of Processor ................................................... 1-1

Portable Low-Power Architecture ............................................. 1-3

System Integration ................................................................... 1-3

Peripherals .................................................................................... 1-4

Contents

iv ADSP-BF50x Blackfin Processor Hardware Reference

Memory Architecture .................................................................... 1-4

Internal Memory ..................................................................... 1-6

External Memory .................................................................... 1-6

I/O Memory Space .................................................................. 1-7

DMA Support .............................................................................. 1-8

General-Purpose I/O (GPIO) ........................................................ 1-9

Two-Wire Interface ..................................................................... 1-10

RSI Interface .............................................................................. 1-11

General-Purpose (GP) Counter ................................................... 1-12

3-Phase PWM Unit .................................................................... 1-13

Parallel Peripheral Interface ......................................................... 1-14

SPORT Controllers .................................................................... 1-16

Serial Peripheral Interface (SPI) Ports .......................................... 1-18

Timers ........................................................................................ 1-18

UART Ports ............................................................................... 1-19

Controller Area Network (CAN) Interface ................................... 1-21

ACM Interface ........................................................................... 1-22

Internal ADC ............................................................................. 1-22

Watchdog Timer ......................................................................... 1-23

Clock Signals .............................................................................. 1-23

Dynamic Power Management ...................................................... 1-24

Full-On Operating Mode—Maximum Performance ............... 1-24

Active Operating Mode—Moderate Dynamic Power Savings .. 1-24

Sleep Operating Mode—High Dynamic Power Savings .......... 1-25

ADSP-BF50x Blackfin Processor Hardware Reference v

Contents

Deep Sleep Operating Mode—Maximum Dynamic Power

Savings ............................................................................... 1-26

Hibernate State—Maximum Static Power Savings ................... 1-26

Instruction Set Description ......................................................... 1-27

Development Tools ..................................................................... 1-28

MEMORY

Memory Architecture .................................................................... 2-1

L1 Instruction SRAM .................................................................... 2-2

L1 Data SRAM ............................................................................. 2-3

L1 Data Cache .............................................................................. 2-4

Boot ROM ................................................................................... 2-4

External Memory .......................................................................... 2-4

Processor-Specific MMRs .............................................................. 2-5

DMEM_CONTROL Register ................................................. 2-5

DTEST_COMMAND Register ............................................... 2-6

CHIP BUS HIERARCHY

Chip Bus Hierarchy Overview ....................................................... 3-1

Interface Overview ........................................................................ 3-2

Internal Clocks ........................................................................ 3-2

Core Bus Overview .................................................................. 3-4

Peripheral Access Bus (PAB) ..................................................... 3-5

PAB Arbitration .................................................................. 3-6

PAB Agents (Masters, Slaves) ............................................... 3-6

PAB Performance ................................................................ 3-7

Contents

vi ADSP-BF50x Blackfin Processor Hardware Reference

DMA Access Bus (DAB), DMA Core Bus (DCB), DMA

External Bus (DEB) .............................................................. 3-7

DAB, DCB, and DEB Arbitration ....................................... 3-7

DAB Bus Agents (Masters) .................................................. 3-9

DAB, DCB, and DEB Performance ..................................... 3-9

External Access Bus (EAB) .................................................... 3-10

Arbitration of the External Bus .............................................. 3-10

DEB/EAB Performance ......................................................... 3-10

SYSTEM INTERRUPTS

Specific Information for the ADSP-BF50x ..................................... 4-1

Overview ...................................................................................... 4-1

Features .................................................................................. 4-2

Description of Operation .............................................................. 4-2

Events and Sequencing ............................................................ 4-2

System Peripheral Interrupts .................................................... 4-4

Programming Model ..................................................................... 4-7

System Interrupt Initialization ................................................. 4-8

System Interrupt Processing Summary ..................................... 4-8

System Interrupt Controller Registers .......................................... 4-10

System Interrupt Assignment (SIC_IAR) Register .................. 4-11

System Interrupt Mask (SIC_IMASK) Register ...................... 4-12

System Interrupt Status (SIC_ISR) Register ........................... 4-12

System Interrupt Wakeup-Enable (SIC_IWR) Register ........... 4-12

ADSP-BF50x Blackfin Processor Hardware Reference vii

Contents

Programming Examples ............................................................... 4-13

Clearing Interrupt Requests ................................................... 4-13

Unique Information for the ADSP-BF50x Processor .................... 4-15

Interfaces .............................................................................. 4-15

System Peripheral Interrupts .................................................. 4-18

EXTERNAL BUS INTERFACE UNIT

EBIU Overview ............................................................................ 5-1

Block Diagram ........................................................................ 5-3

Internal Memory Interfaces ...................................................... 5-4

Registers .................................................................................. 5-4

Error Detection ....................................................................... 5-5

AMC Overview and Features ......................................................... 5-5

Features ................................................................................... 5-6

Asynchronous Memory Interface .............................................. 5-6

Asynchronous Memory Address Decode .............................. 5-6

AMC Description of Operation ..................................................... 5-6

Avoiding Bus Contention ........................................................ 5-6

AMC Programming Model ............................................................ 5-7

EBIU Registers ............................................................................. 5-9

EBIU_AMGCTL Register ..................................................... 5-10

EBIU_AMBCTL Register ...................................................... 5-11

EBIU_MODECTL Register .................................................. 5-12

EBIU_FCTL Register ............................................................ 5-12

Contents

viii ADSP-BF50x Blackfin Processor Hardware Reference

INTERNAL FLASH MEMORY

Overview ...................................................................................... 6-1

Command Interface to Internal Flash Memory .............................. 6-6

Command Interface – Standard Commands ............................ 6-7

Read Array Command ....................................................... 6-7

Read Status Register Command ......................................... 6-8

Read Electronic Signature Command ................................. 6-8

Read CFI Query Command ............................................... 6-9

Clear Status Register Command ......................................... 6-9

Block Erase Command ..................................................... 6-10

Program Command ......................................................... 6-11

Program/Erase Suspend Command ................................... 6-11

Program/Erase Resume Command ................................... 6-12

Protection Register Program Command ............................ 6-13

The Set Configuration Register Command ....................... 6-14

Block Lock Command ..................................................... 6-14

Block Unlock Command ................................................. 6-15

Block Lock-Down Command ........................................... 6-15

Status Register ..................................................................... 6-18

Program/Erase Controller Status Bit (SR7) ....................... 6-19

Erase Suspend Status Bit (SR6) ........................................ 6-20

Erase Status Bit (SR5) ...................................................... 6-20

Program Status Bit (SR4) ................................................. 6-21

VPP Status Bit (SR3) ........................................................ 6-21

ADSP-BF50x Blackfin Processor Hardware Reference ix

Contents

Program Suspend Status Bit (SR2) .................................... 6-22

Block Protection Status Bit (SR1) ..................................... 6-22

Bank Write Status Bit (SR0) ............................................. 6-22

Configuration Register ......................................................... 6-24

Read Select Bit (CR15) .................................................... 6-24

X Latency Bits (CR13-CR11) ........................................... 6-25

Wait Polarity Bit (CR10) .................................................. 6-25

Data Output Configuration Bit (CR9) ............................. 6-26

Wait Configuration Bit (CR8) .......................................... 6-27

Burst Type Bit (CR7) ....................................................... 6-27

Valid Clock Edge Bit (CR6) ............................................. 6-27

Wrap Burst Bit (CR3) ...................................................... 6-27

Burst Length Bits (CR2-CR0) .......................................... 6-27

Read Modes ......................................................................... 6-33

Asynchronous Read Mode ................................................ 6-33

Synchronous Burst Read Mode ......................................... 6-33

Synchronous Burst Read Suspend ..................................... 6-35

Single Synchronous Read Mode ........................................ 6-36

Dual Operations and Multiple Bank Architecture .................. 6-36

Contents

x ADSP-BF50x Blackfin Processor Hardware Reference

Block Locking ...................................................................... 6-38

Reading a Block’s Lock Status .......................................... 6-39

Locked State .................................................................... 6-39

Unlocked State ................................................................ 6-39

Lock-Down State ............................................................. 6-40

Locking Operations During Erase Suspend ....................... 6-40

Block Address Table .................................................................... 6-42

Common Flash Interface ............................................................ 6-45

Flowcharts and Pseudo Codes .................................................... 6-56

Command Interface State Tables ................................................ 6-68

Internal Flash Memory Programming Guidelines ......................... 6-77

Bringing Internal Flash Memory Out of Reset ........................ 6-78

Timing Configurations for Setting the Internal Flash Memory

in Asynchronous Read Mode .............................................. 6-79

Timing Configurations for Setting the Internal Flash Memory

for Write Accesses ............................................................... 6-80

Enabling the Program or Erasure of Internal Flash Memory

Blocks ................................................................................ 6-82

Configuring Internal Flash Memory for Synchronous Burst

Read Mode ......................................................................... 6-83

Supported Configuration Register Combinations in

ADSP-BF50xF Processors .............................................. 6-84

Configuring the EBIU for Synchronous Read Mode .......... 6-85

Unsupported Programming Practices in Flash ........................ 6-87

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