Analog Devices ADAU1962 Manual de usuario

Evaluation Board User Guide

UG-416

One Technology Way •P. O. Box 9106 •Norwood, MA 02062-9106, U.S.A. •Tel: 781.329.4700 •Fax: 781.461.3113 •www.analog.com

Evaluating the ADAU1962/ADAU1966 High Performance,

Low Power, Multibit Sigma-Delta DACs

PACKAGE CONTENTS

ADAU1962/ADAU1966 evaluation board

USBi control interface board

USB cable

D-sub 25-pin to (8) XLR male

12 V desktop supply

OTHER SUPPORTING DOCUMENTATION

ADAU1962 data sheet

ADAU1966 data sheet

EVALUATION BOARD OVERVIEW

This user guide details the design and setup of the evaluation

board for the ADAU1962/ADAU1966. Because the ADAU1962

is a 12-channel device and the ADAU1966 is a 16-channel

device, the DAC 13 through DAC 16 outputs do not function

on the ADAU1962 evaluation board. The evaluation board must

be connected to an external 12 V dc power supply and ground; the

board draws approximately 150 mA.

On-board regulators derive 9 V, 5 V, and 3.3 V supplies for the

ADAU1962/ADAU1966 and peripherals. The ADAU1962/

ADAU1966 can be controlled through either an I2C or SPI

interface. A small external interface board, E VA L -ADUSB2EBZ,

also called an USBi, connects to a PC USB port and provides

either I2C or SPI access to the evaluation board through a ribbon

cable. A graphical user interface (GUI) program, the Automated

the chip in a Microsoft® Windows® PC environment. The

evaluation board allows demonstration and performance testing

of most ADAU1962/ADAU1966 features, including high

performance digital-to-analog converter (DAC) operation.

The board has an S/PDIF receiver with RCA and optical

connectors, as well as a discrete serial audio interface that is

available on the Analog Devices, Inc. system development

platform (SDP) interface. Analog outputs are accessible with two

D-sub, 25-pin connectors using the professional audio standard. A

single D-sub, 25-pin to XLR male cable is included with the board

for connecting individual DAC channels to an audio system.

EVALUATION BOARD DIAGRAM

Figure 1.

S/PDIF

INTERFACE

DSP

INTERFACE

CONTROL

INTERFACE

CLOCK

AND

DATA

ROUTING

DAC 9 TO

DAC 16

DAC 1 TO

DAC 8

POWER SUPPLY

ADAU1966/

ADAU1962

10717

-001

PLEASE SEE THE LAST PAGE FOR AN IMPORTANT

WARNING AND LEGAL TERMS AND CONDITIONS.Rev. A | Page 1 of 28

UG-416 Evaluation Board User Guide

TABLE OF CONTENTS

Package Contents.............................................................................. 1

Other Supporting Documentation................................................. 1

Evaluation Board Overview ............................................................ 1

Evaluation Board Diagram.............................................................. 1

Revision History ............................................................................... 2

Setting Up the Evaluation Board .................................................... 3

Standalone Mode.......................................................................... 3

I2C and SPI Control...................................................................... 4

Automated Register Window Builder Software Installation .. 4

Hardware Setup—USBi ............................................................... 4

Powering the Board.......................................................................5

Reset for the Evaluation Board....................................................5

Setting Up the Master Clock (MCLK)........................................6

Crystal Operation..........................................................................6

PLL Selection .................................................................................7

Digital Audio Connections and Routing ...................................7

Connecting Analog Audio Cables ..............................................8

Using the ADAU1962/ADAU1966 .............................................8

Schematics and Artwork ..................................................................9

REVISION HISTORY

1/14—Rev. 0 to Rev. A

Added ADAU1962..............................................................Universal

Changes to Evaluation Board Overview Section and Figure 1 .. 1

5/12—Revision 0: Initial Version

Rev. A | Page 2 of 28

Evaluation Board User Guide UG-416

SETTING UP THE EVALUATION BOARD

STANDALONE MODE

The ADAU1962/ADAU1966 have a standalone mode that allows

the user to choose between a limited number of operation modes

without the need for a control interface. Applying a jumper across

JP21, as shown in Figure 2, pulls SA_MODE (Pin 46) high,

enabling the standalone mode in the ADAU1962/ADAU1966.

The SA_MODE selections are listed in Table 1.

Table 1. Standalone Modes

Pin(s) Jumper Setting Description

42 0 Serial audio interface, master mode

1 Serial audio interface, slave mode

43 0 MCLK select: 256 × fS, PLL

1 MCLK select: 384 × fS, PLL

44 0 CM = 2.25 V (for AVDD = 5 V)

1 CM = 1.50 V (for AVDD = 3.3 V)

45 0 Serial audio interface, I2S mode

1 Serial audio interface, TDM mode

32:31 00 TDM4, pulse

01 TDM8, pulse

10 TDM16, pulse

11 TDM8, 50% duty

On the ADAU1962/ADAU1966 evaluation board, each of the four

ADAU1962/ADAU1966 control port pins is brought to a block of

jumpers, allowing each pin to be assigned to either the I2C port or

the SPI port. In standalone mode, these jumpers can connect the

individual pins to high or low to put the ADAU1962/ADAU1966

in the desired mode.

Figure 2. SA_MODE—Slave, 256 × fS, CM = 2.25 V, I2S

The ADAU1962/ADAU1966 evaluation board arrives configured

for S/PDIF input. The S/PDIF receiver operates as a clock master,

putting out an I2S stream at 256 × fS. For a quick startup, the

ADAU1962/ADAU1966 are in standalone mode with the settings

shown in Figure 2. Pin 42 is pulled high (1) and Pin 43 to Pin 45 are

pulled low (0). According to Table 1, this puts the ADAU1962/

ADAU1966 in slave mode, running at 256 × fS, while common

mode (CM) is set to 2.25 V and the audio serial port is in I2S mode.

Notice in Figure 2 that the jumper for Pin 42 is assigned to 1 and

that the other pins are assigned to 0.

Figure 3. SA_MODE—Master, 384 × fS, CM = 1.50 V, TDM

Figure 3 shows the other options for each SA_MODE configuration

pin; master mode, running at 384 × fS, CM set to 1.50 V, and

the audio serial port in TDM mode. In the case where the

ADAU1962/ADAU1966 are put in TDM mode, Pin 31 and

Pin 32 can be pulled high or low to achieve the modes listed in

Table 1. The correct pins are outlined in the top left corner of

Figure 3, as DSD8 and DSD7.

10717-002

10717-003

Rev. A | Page 3 of 28

UG-416 Evaluation Board User Guide

I2C AND SPI CONTROL

The evaluation board can be configured for live control over

the registers in the ADAU1962/ADAU1966. When the

Automated Register Window Builder software is installed

and the USBi control interface is plugged into the board, the

software can control the ADAU1962/ADAU1966. For this

configuration, the ADAU1962/ADAU1966 must be assigned to

I2C mode using Address 00. See Figure 4 for the correct jumper

positions.

Figure 4. ADAU1962/ADAU1966 I2C Control, Address 00

The Automated Register Window Builder controls the

ADAU1962/ADAU1966 and is available for download under

the Tools, Software, & Simulation Models section of the

ADAU1962 and ADAU1966 product pages.

In addition, the ADAU1962/ADAU1966 can be put into SPI

mode for control by other means. See Figure 5 for the correct

jumper positions.

Figure 5. ADAU1962/ADAU1966 SPI Control

AUTOMATED REGISTER WINDOW BUILDER

SOFTWARE INSTALLATION

The Automated Register Window Builder is a program that

launches a graphical interface for direct, live control of the

ADAU1962/ADAU1966 registers. The GUI content for a

specific part is defined in a part-specific .xml file; these files are

included in the software installation. To install the Automated

1. Go to the ADAU1962 and ADAU1966 product pages and

download the 64-Bit OS (ARWB_64BIT.zip) or 32-Bit OS

(ARWB_32Bit.zip) file, which can be found under the

Tools, Software, & Simulation Models section of the

ADAU1962 and ADAU1966 product pages.

2. Open the downloaded.zip file and extract the files to an

empty folder on your PC.

3. Install the Automated Register Window Builder by

double-clicking setup.exe and following the prompts. A

computer restart is not required.

4. Copy the .xml file for the ADAU1962/ADAU1966 from the

extraction folder into the C:\ProgramFiles\Analog

Devices Inc\AutomatedRegWin folder, if it is not already

installed.

HARDWARE SETUP—USBi

To set up the USBi hardware, follow these steps:

1. Plug the USBi ribbon cable into J12, the I2C/SPI port.

2. Connect the USB cable to the PC and to the USBi.

3. When prompted for drivers, follow these steps:

a. Choose Install from a list or a specific location.

b. Choose Search for the best driver in these locations.

c. Check the box for Include this location in the search.

d. Find the USBi driver C:\Program Files\Analog

Devices Inc\AutomatedRegWin\USB drivers.

e. Click Next.

f. If prompted to choose a driver, select CyUSB.sys.

g. If the PC is running Windows XP and a message

appears saying that the software has not passed

Windows logo testing, click Continue Anyway.

4. Open the Automated Register Window Builder application

and load the .xml file for the part on the evaluation board.

Plug the 10-way ribbon cable on the USBi into the I2C/SPI

port (J12) on the evaluation board.

10717-004

10717-005

Rev. A | Page 4 of 28

Evaluation Board User Guide UG-416

POWERING THE BOARD

The ADAU1962/ADAU1966 evaluation board requires a power

supply input of 12 V dc and ground to the power jack; 12 V

draws ~150 mA at higher sample rates with all channels running.

The on-board regulators provide 9.0 V, 5.0 V, and 3.3 V rails. The

9.0 V rail is derived from 12 V by a linear regulator; it provides

voltage to the audio op amp in the active output filter for

Channel 1 and Channel 2. The 5.0 V rail is derived from 12 V

by a switching regulator; it can supply AVDD as well as IOVDD

for the ADAU1962/ADAU1966 and other peripherals. The 3.3 V

rail is derived from the 5.0 V supply by an LDO linear regulator;

it provides voltage to AVDD and IOVDD as well as other active

peripherals.

AVDD and IOVDD are selected on the board using 0 Ω, 0805

package resistors. Install only one resistor for each load, AVDD

and IOVDD, as described in Figure 6. Figure 6 shows AVDD

fed from 5.0 V and IOVDD fed from 3.3 V.

Figure 6. AVDD and IOVDD Selection Resistors

The ADAU1962/ADAU1966 have an internal voltage regulator

that allows the user to derive DVDD and PLLVDD from the

AVDD voltage source. The external PNP transistor, Q1, and

passives, C36, C40 and R56, make the regulator circuit shown in

Figure 7. Short both JP9 and JP11 to activate the circuit; JP9

supplies the emitter of the PNP, and JP11 powers the VSUPPLY

pin (Pin 25) on the ADAU1962/ADAU1966.

Figure 7. ADAU1962/ADAU1966 Internal Regulator Jumpers

Links are provided along each ADAU1962/ADAU1966 power rail

to give access for current measurement (see Figure 8). These

links also allow directly supplying voltage from an outside

source.

Figure 8. ADAU1962/ADAU1966 Power Links

RESET FOR THE EVALUATION BOARD

The ADAU1962/ADAU1966 evaluation board has provision for

resetting and powering down the ADAU1962/ADAU1966. S2 on

the evaluation board, shown in Figure 9, is a momentary reset

switch that pulls the master reset (MR) line low; this line

controls the reset generator U10. MR is also connected to the

USBi and SDP INTF connectors through steering diodes and

protection resistors so that outside devices can control the reset

state of the evaluation board, as shown in Figure 26. The power

down jumper, JP5, allows the MR line to be tied low. The output

of the reset generator drives the PU_/RST line.

The PU_/RST line is directly connected to two devices: the S/PDIF

receiver and the ADAU1962/ADAU1966. A pull-down resistor

holds the line low until the reset generator, U10, asserts the line

high, as shown in Figure 26. The PU_/RST line is also connected

to a pin on the SDP INTF through a steering diode and protection

resistor, allowing external reset control.

Figure 9. RESET Switch and Power-Down Jumper

10717-006

10717-007

10717-008

10717-009

Rev. A | Page 5 of 28

UG-416 Evaluation Board User Guide

SETTING UP THE MASTER CLOCK (MCLK)

The MCLK routing on the evaluation board is handled by a block

of jumpers, J5, allowing any one of four sources to be selected:

SPDIF, SMA connector, active OSC, and INTF connector. The

board comes with SPDIF selected, as shown in Figure 10.

Figure 10. SPDIF Selected as MCLK Source

The evaluation board has a 12.288 MHz active oscillator that

can be selected by shorting the OSC_EN jumper, JP8, and

selecting OSC on J5, as shown in Figure 11.

Figure 11. Active OSC-Enabled and Selected as MCLK

When using the SDP interface to add serial audio onto the

evaluation board, MCLK can either be supplied by the SDP

board, or it can be supplied by the MCLKO pin of the

ADAU1962/ADAU1966.

To route MCLK from the SDP interface to the ADAU1962/

ADAU1966, apply a shorting jumper across JP6 (MCLK_SEL),

as shown in Figure 12; this sets the direction of the level

translators on the board to receive an MCLK signal from the

SDP interface, EI3 1A, Pin 119 (EI3_MCLK), as shown in

Figure 28. Next, select INTF on JP5 to route the output of

the MCLK level translator to the MCLKI pin of the

ADAU1962/ADAU1966.

Figure 12. INTF Input Enabled and Selected

To route MCLK from the ADAU1962/ADAU1966 to the SDP

interface, remove the shorting jumper from JP6 (MCLK_SEL); this

changes the direction of the level translators and feeds a buffered

version of the MCLKO signal from the ADAU1962/ADAU1966 to

the EI3_MCLK pin on the SDP interface.

CRYSTAL OPERATION

The ADAU1962/ADAU1966 evaluation board is shipped

without R49 on the board, effectively disabling the crystal circuit.

For operation with a crystal, install a 150 Ω, 0402 resistor and

remove any jumpers from J5. For permanent use of the crystal,

remove the 0 Ω resistor, R39.

Figure 13. Crystal Circuit Near ADAU1962/ADAU1966

10717-010

10717-011

10717-012

10717-013

Rev. A | Page 6 of 28

Evaluation Board User Guide UG-416

PLL SELECTION

The PLL in the ADAU1962/ADAU1966 is very flexible,

allowing the part to run from a wide range of either MCLK or

LRCLK frequencies. It is also possible to shut the PLL off

altogether and use the part in direct MCLK mode; functionality

with no PLL is limited to 256 × fS.

By default, the ADAU1962/ADAU1966 run from the PLL using

MCLK as the clock source. The MCLK loop filter must be

selected using JP2, as shown in Figure 14.

Figure 14. MCLK Selection for PLL Loop Filter

DLRCLK can be selected as the PLL clock source using the PLL

and Clock Control Register 0, Register 0x00, Bits[7:6]. In this

case, the LRCLK loop filter must be selected, as shown in Figure 15.

If DLRCLK is selected as the PLL clock, there is no need for an

MCLK signal.

Figure 15. LRCLK Selection for PLL Loop Filter

DIGITAL AUDIO CONNECTIONS AND ROUTING

The ADAU1962/ADAU1966 evaluation board has two separate

inputs for digital audio signals: S/PDIF and SDP interface.

The S/PDIF receiver can handle either of two options: COAX

uses the RCA jack, J1, and OPT uses the Toslink jack, U1. The

S/PDIF input is selected using S1, as shown in Figure 16.

Figure 16. S/PDIF Input Selector Switch, SW1

A series of resistors is provided to set the functional mode of the

S/PDIF receiver. By default, the S/PDIF receiver runs in master

mode, 256 × fS, I2S format; consult the data sheet for the S/PDIF

receiver to make changes to the hardware mode.

The jumpers shown in Figure 17 are set for the S/PDIF receiver

to drive the DBCLK and DLRCLK clock ports and the eight

DSDATAx lines of the ADAU1962/ADAU1966. JP22 selects the

input to the buffer; the output of this buffer shows up on the right-

hand column of JP13 to JP20. The pins in the middle column of

these jumpers are connected to the DSDATAx pins of the

ADAU1962/ADAU1966 through the appropriate line termination.

DBCLK and DLRCLK selections are made with JP10 and JP12,

respectively, where the middle pins are connected to the

DBCLK and DLRCLK pins of the ADAU1962/ADAU1966.

Figure 17. S/PDIF Data and Clock Routing

The SDP interface, J6 and J8, make up a standard interconnect

within Analog Devices. They provide for transfer of digital audio,

clocks, and control between boards. For additional information,

see the pinout included in the schematic in Figure 28.

10717-014

10717-015

10717-016

10717-017

Rev. A | Page 7 of 28

UG-416 Evaluation Board User Guide

Figure 18 shows the jumpers configuration for using the SDP

interface connector as the digital audio source. JP22 is set so

that the DSDATA1 source from the SDP interface is driving the

buffer, and this buffer is connected to all eight/six DSDATAx

inputs of the ADAU1962/ADAU1966. JP10 and JP12 are set for

the ADAU1962/ADAU1966 to run in slave mode from clocks

supplied by the SDP interface.

Figure 18. SDP Interface DSDATA1 Distribution

CONNECTING ANALOG AUDIO CABLES

There are two forms of the analog outputs of the ADAU1962/

ADAU1966 evaluation board: differential outputs and single-

ended outputs.

The differential outputs appear on through hole test points as well

as on 25-way, female D-sub connectors. The pinout of these D-sub

connectors follows the professional audio standard for eight

differential signals on a single jack. A single 25-pin male D-sub

to XLR male harness has been provided for testing and evaluation

purposes. These cables are widely available on the open market.

The differential outputs of the ADAU1962/ADAU1966 drive

the connectors directly through a simple 1-pole RC filter and

appropriate ac coupling.

Channel 1 and Channel 2 are also available as single-ended outputs

on a stereo, 3.5 mm stereo jack, J14. The J9 and J10 jumpers assign

the differential outputs of the DAC to either the passive differential

output or the active single-ended filter.

Figure 19 shows J9 and J10 set for the passive differential output

available on the D-sub connector.

Figure 19. Channel 1 and Channel 2 in Passive Differential Output Mode

Figure 20. Channel 1 and Channel 2 in Active Single-Ended Output Mode

Figure 20 shows J9 and J10 set for the active single-ended output

available on the 3.5 mm TRS connector, J14.

USING THE ADAU1962/ADAU1966

When the ADAU1962/ADAU1966 start in standalone mode, it is

operational upon power up.

If the ADAU1962/ADAU1966 are not powered up in

standalone mode, the USBi must be connected to set the

appropriate registers to make the part operational. First, the

ADAU1962/ADAU1966 must be activated using the PLL and

Clock Control 0 register (Address 0x00) by setting the PUP bit

(Bit 0) to 1 for master power-up. Next, using the DAC Control 0

normal operation. The ADAU1962/ADAU1966 now pass audio

in its default mode: I2S, 256 × fS, slave mode, and CM = 2.25 V.

If different settings are desired, it is recommended to program

the custom settings before unmuting the part.

10717-018

10717-019

10717-020

Rev. A | Page 8 of 28

Evaluation Board User Guide UG-416

SCHEMATICS AND ARTWORK

Figure 21. ADAU1962/ADAU1966 Evaluation Board Block Diagram Schematic, Page 1

ADAU1966

DAC Diff Out 3-8 Passive RC 1 pole

DAC Diff Out 9-16 Passive RC 1 pole

1 Pole Passive 1 Pole Active

DAC Diff Out 1-2 Passive RC 1 Pole

DAC SE Out 1-2 Active Filter

Power Supply Regulators

5v0 = Switching Supply

3v3 = Linear Supply derived from 5v0

Int Reg

Xistor

DVDD

PLLVDD

AVDD = 5v0 / 3v3

IOVDD = 5v0 / 3v3

Single jumpers for each supply

for current measurement

MCLK Sources

SPDIF

Crystal

DSP Intf

EXT In

Active OSC

USBi Control port

SA_Mode Jumps

COM Port Jumps

PD Jump

SPDIF Receiver

DSP/FPGA Interface

BCLK, LRCLK

SDATA Jumps

with Buffer

12 VDC

Input

Optical and Coax In

Allows for Direct

Connect to DUT

SE output on TRS Mini Jack

Diff Outs on d-sub 25

Reset Switch

3v3 for SPDIF Core

IOVDD comes from DUT IOVDD

Control Jumpers

Hardware Mode

Desktop Supply

CM Output on TP

Buffered MCLKO

OP AMP = 9v0 Linear Adjustable

CLKs

CLKs and DATA

3v3 / 2v5

IOVDD and AVDD select using 0R00

24 VDC Input MAX!

10717-021

Rev. A | Page 9 of 28

UG-416 Evaluation Board User Guide

Figure 22. ADAU1962/ADAU1966 Evaluation Board, PLL LF Selection and Internal Regulator Schematic, Page 2

Enable

ADAU1966 Voltage Regulator

MCLK LRCLK

See pages5&6 for jumpers

Stand-Alone Modes

Master SAI

Slave SAI

256xFs, PLL

382xFs,PLL

CM=2v25

CM=1v50

I2S

TDM

TDM4, Pulse

TDM8, Pulse

TDM16, Pulse

TDM8, 50% Duty Cycle

Pin 42

Pin 43

Pin 44

Pin 45

Pins 32:31

C76

0.47uF

C37

C68 C65

C77

C43

0.47uF

C72

0.47uF

C45

0.47uF

C75

C41

C71 C67

C42

C47

C44C53

JP1

JP3

C134

10uF

C130

10uF

TP66 TP63

TP26

TP21

TP25

TP44

ZX5T953GTA

C36C40

C126

10uF

R56

1k50

TP50

TP53

C18

2.2nF NP0

C21

39nF

R25

3k32

JP2

C17

390pF

C20

5.6nF

R27

562R

2221 2423 2625

27 28

J11

HEADER_28WAY_UNSHROUD

C125

10uF

C127

10uF

C129

10uF

JP11

C128

10uF

C131

10uF

C133

10uF

27 DBCLK

28 DLRCLK

31 DSDATA8

32 DSDATA7

33 DSDATA6

34 DSDATA5

35 DSDATA4

36 DSDATA3

37 DSDATA2

38 DSDATA1

30DGND

21 DGND

19 MCLKO

18 XTALO

17 MCLKI/XTALI

16 PLLVDD

15 LF

14 PLLGND

47 PU/RST

46 SA_MODE

45 CLATCH/ADDR0

44 CCLK/SCL

43 COUT/SDA

42 CDATA/ADDR1

DAC1P 51

DAC1N

DAC2P 53

DAC2N

DAC3P 55

DAC3N

DAC4P 57

DAC4N

DAC_BIAS1 60

DAC_BIAS2

DAC5P 65

DAC5N

DAC6P 67

DAC6N

DAC7P 69

DAC7N

DAC8P 71

DAC8N

DAC9P 73

DAC9N

DAC10P 75

DAC10N

DAC11P 77

DAC11N

DAC12P 79

DAC12N

DAC_BIAS3 2

DAC_BIAS4

DAC13P 5

DAC13N

TS_REF 62

40DGND

VDRIVE

VSENSE

VSUPPLY

IOVDD

DVDD

IOVDD

DVDD

AVDD4

AVDD3

AVDD2

AVDD1

DVDD

DAC14P 7

DAC14N

DAC15P 9

DAC15N

DAC16P11

DAC16N

13 AGND4

80 AGND3

61AGND2

48 AGND1

26 DGND

ADAU1966WBSTZ

JP21

R138

10k0

TP57

JP9

JP7

JP4

TP27

TP45 TP71

[2]1966_CDATA/ADDR1

[2]1966_COUT/SDA

[2]1966_CCLK/SCL

[2]1966_CLATCH/ADDR0

[6,9] PU_RST

[3]

DAC1P [3]

DAC1N

[3]

DAC2P [3]

DAC2N

[3]

DAC3P [3]

DAC3N

[3]

DAC4P [3]

DAC4N

TS_REF

[4]

DAC5P [4]

DAC5N

[4]

DAC6P [4]

DAC6N

[4]

DAC7P [4]

DAC7N

[4]

DAC8P [4]

DAC8N

[4]

DAC9P [4]

DAC9N

[4]

DAC10P [4]

DAC10N

[4]

DAC11P [4]

DAC11N

[4]

DAC12P [4]

DAC12N

[4]

DAC13P [4]

DAC13N

[4]

DAC14P [4]

DAC14N

[4]

DAC15P [4]

DAC15N

[4]

DAC16P [4]

DAC16N

[6] MCLKI/XTALI

[2]

VDRIVE

[2]

VSENSE

[2]

VSUPPLY

AVDD

IOVDD

[2]

VSENSE

[2]

VSUPPLY

[2]

VDRIVE

[2]

VSENSE

[2]

VSENSE

1966_IOVDD

1966_DVDD

AVDD

PLLVDD

USBI_CDATA

[6] XTALO

[6] MCLKO

IOVDD

[5] 1966_DSDATA1

[5] 1966_DSDATA2

[5] 1966_DSDATA3

[5] 1966_DSDATA4

[5] 1966_DSDATA8

[5] 1966_DSDATA7

[5] 1966_DSDATA6

[5] 1966_DSDATA5

[5]1966_DLRCLK

[5]1966_DBCLK

SA_MODE

[2]

1966_CLATCH/ADDR0

[2]

1966_COUT/SDA

[2]

1966_CCLK/SCL

[6,7] USBI_CLATCH_A

[6,7] USBI_CCLK

[6,7] USBI_SCL

[2]

1966_AVDD

[2]

1966_CDATA/ADDR1

[6,7] USBI_COUT

[6,7] USBI_SDA

[2,6,7] USBI_CDATA

IOVDD

10717-022

Rev. A | Page 10 of 28

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