Altera EP2AGX45 Guía de aplicación

December 2010 Altera Corporation Arria II Device Handbook Volume 1: Device Interfaces and Integration

Section I. Device Core for Arria II Devices

This section provides a complete overview of all features relating to the Arria®II

device family, the industry’s first cost-optimized 40 nm FPGA family. This section

includes the following chapters:

■Chapter 1, Overview for the Arria II Device Family

■Chapter 2, Logic Array Blocks and Adaptive Logic Modules in Arria II Devices

■Chapter 3, Memory Blocks in Arria II Devices

■Chapter 4, DSP Blocks in Arria II Devices

■Chapter 5, Clock Networks and PLLs in Arria II Devices

Revision History

Refer to each chapter for its own specific revision history. For information on when

each chapter was updated, refer to the Chapter Revision Dates section, which appears

in this volume.

I–2 Section I: Device Core for Arria II Devices

Revision History

Arria II Device Handbook Volume 1: Device Interfaces and Integration December 2010 Altera Corporation

Arria II Device Handbook Volume 1: Device Interfaces and Integration

December 2010

AIIGX51001-4.0

and/or trademarks of Altera Corporation in the U.S. and other countries. All other trademarks and service marks are the property of their respective holders as described at

www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but

reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability aris ing out of the application or use of any

information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device

specifications before relying on any published information and before placing orders for products or services.

1. Overview for the Arria II Device Family

The Arria®II device family is designed specifically for ease-of-use. The

cost-optimized, 40-nm device family architecture features a low-power,

programmable logic engine and streamlined transceivers and I/Os. Common

interfaces, such as the Physical Interface for PCI Express®(PIPE) (PCIe®), Ethernet,

and DDR3 memory are easily implemented in your design with the Quartus®II

software, the SOPC Builder design software, and a broad library of hard and soft

intellectual property (IP) solutions from Altera®. The Arria II device family makes

designing for applications requiring transceivers operating at up to 6.375 Gbps fast

and easy.

This chapter contains the following sections:

■“Arria II Device Feature” on page 1–1

■“Arria II Device Architecture” on page 1–6

■“Reference and Ordering Information” on page 1–14

Arria II Device Feature

The Arria II device features consist of the following highlights:

■40-nm, low-power FPGA engine

■Adaptive logic module (ALM) offers the highest logic efficiency in the industry

■Eight-input fracturable look-up table (LUT)

■Memory logic array blocks (MLABs) for efficient implementation of small

FIFOs

■High-performance digital signal processing (DSP) blocks up to 550 MHz

■Configurable as 9 × 9-bit, 12 × 12-bit, 18 × 18-bit, and 36 × 36-bit full-precision

multipliers as well as 18 × 36-bit high-precision multiplier

■Hardcoded adders, subtractors, accumulators, and summation functions

■Fully-integrated design flow with the MATLAB and DSP Builder software

from Altera

December 2010

AIIGX51001-4.0

1–2 Chapter 1: Overview for the Arria II Device Family

Arria II Device Feature

Arria II Device Handbook Volume 1: Device Interfaces and Integration December 2010 Altera Corporation

■Maximum system bandwidth

■Up to 24 full-duplex clock data recovery (CDR)-based transceivers supporting

rates between 155 Mbps and 6.375 Gbps

■Dedicated circuitry to support physical layer functionality for popular serial

protocols, including PCIe Gen1 and PCIe Gen2, Gbps Ethernet, Serial

RapidIO®(SRIO), Common Public Radio Interface (CPRI), OBSAI,

SD/HD/3G/ASI Serial Digital Interface (SDI), XAUI and Reduced XAUI

(RXAUI), HiGig/HiGig+, SATA/Serial Attached SCSI (SAS), GPON,

SerialLite II, Fiber Channel, SONET/SDH, Interlaken, Serial Data Converter

(JESD204), and SFI-5.

■Complete PIPE protocol solution with an embedded hard IP block that provides

physical interface and media access control (PHY/MAC) layer, Data Link layer,

and Transaction layer functionality

■Optimized for high-bandwidth system interfaces

■Up to 726 user I/O pins arranged in up to 20 modular I/O banks that support a

wide range of single-ended and differential I/O standards

■High-speed LVDS I/O support with serializer/deserializer (SERDES) and

dynamic phase alignment (DPA) circuitry at data rates from 150 Mbps to

1.25 Gbps

■Low power

■Architectural power reduction techniques

■Typical physical medium attachment (PMA) power consumption of 100 mW at

3.125 Gbps.

■Power optimizations integrated into the Quartus II development software

■Advanced usability and security features

■Parallel and serial configuration options

■On-chip series (RS) and on-chip parallel (RT) termination with auto-calibration

for single-ended I/Os and on-chip differential (RD) termination for differential

I/O

■256-bit advanced encryption standard (AES) programming file encryption for

design security with volatile and non-volatile key storage options

■Robust portfolio of IP for processing, serial protocols, and memory interfaces

■Low cost, easy-to-use development kits featuring high-speed mezzanine

connectors (HSMC)

■Emulated LVDS output support with a data rate of up to 1152 Mbps

Chapter 1: Overview for the Arria II Device Family 1–3

Arria II Device Feature

December 2010 Altera Corporation Arria II Device Handbook Volume 1: Device Interfaces and Integration

Table 1–1 lists the Arria II device features.

Table 1–1. Features in Arria II Devices

Feature

Arria II GX Devices Arria II GZ Devices

EP2AGX45 EP2AGX65 EP2AGX95 EP2AGX125 EP2AGX190 EP2AGX260 EP2AGZ225 EP2AGZ300 EP2AGZ350

Total Transceivers (1) 8 8 12 12 16 16 16 or 24 16 or 24 16 or 24

ALMs 18,050 25,300 37,470 49,640 76,120 102,600 89,600 119,200 139,400

LEs 42,959 60,214 89,178 118,143 181,165 244,188 224,000 298,000 348,500

PCIe hard IP blocks 1 1 1 1 1 1 1 1 1

M9K Blocks 319 495 612 730 840 950 1,235 1,248 1,248

M144K Blocks — — — — — — — 24 36

Total Embedded Memory in M9K

Blocks (Kbits) 2,871 4,455 5,508 6,570 7,560 8,550 11,115 14,688 16,416

Total On-Chip Memory

(M9K +M144K + MLABs) (Kbits) 3,435 5,246 6,679 8,121 9,939 11,756 13,915 18,413 20,772

Embedded Multipliers (18 × 18) (2) 232 312 448 576 656 736 800 920 1,040

General Purpose PLLs 4 4 6 6 6 6 6 or 8 4, 6, or 8 4, 6, or 8

Transceiver TX PLLs (3),(4) 2 or 4 2 or 4 4 or 6 4 or 6 6 or 8 6 or 8 8 or 12 8 or 12 8 or 12

User I/O Banks (5), (6) 6 6 8 8 12 12 16 or 20 8, 16, or 20 8, 16, or 20

High-Speed LVDS SERDES

(up to 1.25 Gbps) (7) 8, 24, or 28 8, 24, or 28 24, 28, or 32 24, 28, 32 28 or 48 24 or 48 42 or 86 0 (8), 42, or 86 0 (8), 42, or 86

Notes to Ta ble 1– 1:

(1) The total number of transceivers is divided equally between the left and right side of each device, except for the devices in the F780 package. These devices have eight transceiver channels located only on

the right side of the device.

(2) This is in four multiplier adder mode.

(3) The FPGA fabric can use these phase locked-loops (PLLs) if they are not used by the transceiver.

(4) The number of PLLs depends on the package. Transceiver transmitter (TX) PLL count = (number of transceiver blocks) × 2.

(5) Banks 3C and 8C are dedicated configuration banks and do not have user I/O pins.

(6) For Arria II GZ devices, the user I/Os count from pin-out files includes all general purpose I/O, dedicated clock pins, and dual purpose configuration pins. Transceiver pins and dedicated configuration pins

are not included in the pin count.

(7) For Arria II GZ devices, total pairs of high-speed LVDS SERDES take the lowest channel count of RX/TX.For more information, refer to the High-Speed I/O Interfaces and DPA in Arria II Devices chapter.

(8) The smallest pin package (780-pin package) does not support high-speed LVDS SERDES.

1–4 Chapter 1: Overview for the Arria II Device Family

Arria II Device Feature

Arria II Device Handbook Volume 1: Device Interfaces and Integration December 2010 Altera Corporation

Table 1–2 and Table 1–3 list the Arria II device package options and user I/O pin

counts, high-speed LVDS channel counts, and transceiver channel counts for Ultra

FineLine BGA (UBGA) and FineLine BGA (FBGA) devices.

Table 1–2. Package Options and I/O Information for Arria II GX Devices (Note 1), (2),(3), (4), (5), (6), (7)

Device

358-Pin Flip Chip UBGA

17 mm × 17 mm

572-Pin Flip Chip FBGA

25 mm × 25 mm

780-Pin Flip Chip FBGA

29 mm × 29 mm

1152-Pin Flip Chip FBGA

35 mm × 35 mm

I/O LVDS (8)

XCVRs

I/O LVDS (8)

XCVRs

I/O LVDS (8)

XCVRs

I/O LVDS (8)

XCVRs

EP2AGX45 156

33(RDor eTX)

+ 32(RX, TX,

or eTX)

4252

57(RDor

eTX) +

56(RX, TX,

or eTX)

8364

85(RDor eTX)

+ 84(RX, TX,

or eTX)

8— — —

EP2AGX65 156

33(RDor eTX)

+ 32(RX, TX,

or eTX)

4252

57(RDor

eTX) +

56(RX, TX,

or eTX)

8364

85(RDor eTX)

+84(RX,TX,

eTX)

8— — —

EP2AGX95 — — — 260

57(RDor

eTX) +

56(RX, TX,

or eTX)

8372

85(RDor eTX)

+84(RX, TX, or

eTX)

12 452

105(RDor

eTX) +

104(RX, TX, or

eTX)

EP2AGX125 — — — 260

57(RDor

eTX) +

56(RX,TX, or

eTX)

8372

85(RDor eTX)

+84(RX,TX, or

eTX)

12 452

105(RDor

eTX) +

104(RX, TX, or

eTX)

EP2AGX190 — — — — — — 372

85(RDor eTX)

+84(RX, TX, or

eTX)

12 612

145(RDor

eTX) +

144(RX, TX, or

eTX)

EP2AGX260 — — — — — — 372

85(RD, eTX)

+84(RX, TX, or

eTX)

12 612

145(RD, eTX) +

144(RX, TX, or

eTX)

Notes to Ta ble 1– 2 :

(1) The user I/O counts include clock pins.

(2) The arrows indicate packages vertical migration capability. Vertical migration allows you to migrate to devices whose dedicated pins, configuration pins,

and power pins are the same for a given package across device densities.

(3) RD= True LVDS input buffers with on-chip differential termination (RDOCT) support.

(4) RX = True LVDS input buffers without RDOCT support.

(5) TX = True LVDS output buffers.

(6) eTX = Emulated-LVDS output buffers, either

LVDS_E_3R

LVDS_E_1R

(7) The LVDS channel count does not include dedicated clock input pins and PLL clock output pins.

(8) These numbers represent the accumulated LVDS channels supported in Arria II GX row and column I/O banks.

Chapter 1: Overview for the Arria II Device Family 1–5

Arria II Device Feature

December 2010 Altera Corporation Arria II Device Handbook Volume 1: Device Interfaces and Integration

Arria II devices are available in up to four speed grades: –3 (fastest), –4, –5, and –6

(slowest). Table 1–4 lists the speed grades for Arria II devices.

Table 1–3. Package Options and I/O Information for Arria II GZ Devices (Note 1),(2), (3), (4), (5)

Device

780-Pin Flip Chip FBGA

29 mm × 29 mm

1152-Pin Flip Chip FBGA

35 mm × 35 mm

1517-Pin Flip Chip FBGA

40 mm × 40 mm

I/O LVDS (6)

XCVRs

I/O LVDS (7)

XCVRs

I/O LVDS (7)

XCVRs

EP2AGZ225 — — — 554 135 (RX or eTX) +

140 (TX or eTX) 16 734 179 (RX or eTX) +

184 (TX or eTX) 24

EP2AGZ300 281 68 (RX or eTX) +

72 eTX 16 554 135 (RX or eTX) +

140 (TX or eTX) 16 734 179 (RX or eTX) +

184 (TX or eTX) 24

EP2AGZ350 281 68 (RX or eTX) +

72 eTX 16 554 135 (RX or eTX) +

140 (TX or eTX) 16 734 179 (RX or eTX) +

184 (TX or eTX) 24

Notes to Ta ble 1– 3 :

(1) The user I/O counts include clock pins.

(2) RX = True LVDS input buffers without RDOCT support for row I/O banks, or true LVDS input buffers without RDOCT support for column I/O

banks.

(3) eTX = Emulated-LVDS output buffers, either

LVDS_E_3R

LVDS_E_1R.

(4) The LVDS RX and TX channels are equally divided between the left and right sides of the device.

(5) The LVDS channel count does not include dedicated clock input pins.

(6) For Arria II GZ 780-pin FBGA package, the LVDS channels are only supported in column I/O banks.

(7) These numbers represents the accumulated LVDS channels supported in Arria II GZ device row and column I/O banks.

Table 1–4. Speed Grades for Arria II Devices

Device 358-Pin Flip Chip

UBGA

572-Pin Flip Chip

FBGA

780-Pin Flip Chip

FBGA

1152-Pin Flip Chip

FBGA

1517-Pin Flip Chip

FBGA

EP2AGX45 C4, C5, C6, I5 C4, C5, C6, I3, I5 C4, C5, C6, I3, I5 — —

EP2AGX65 C4, C5, C6, I5 C4, C5, C6, I3, I5 C4, C5, C6, I3, I5 — —

EP2AGX95 — C4, C5, C6, I3, I5 C4, C5, C6, I3, I5 C4, C5, C6, I3, I5 —

EP2AGX125 — C4, C5, C6, I3, I5 C4, C5, C6, I3, I5 C4, C5, C6, I3, I5 —

EP2AGX190 — — C4, C5, C6, I3, I5 C4, C5, C6, I3, I5 —

EP2AGX260 — — C4, C5, C6, I3, I5 C4, C5, C6, I3, I5 —

EP2AGZ225 — — — C3, C4, I3, I4 C3, C4, I3, I4

EP2AGZ300 — — C3, C4, I3, I4 C3, C4, I3, I4 C3, C4, I3, I4

EP2AGZ350 — — C3, C4, I3, I4 C3, C4, I3, I4 C3, C4, I3, I4

1–6 Chapter 1: Overview for the Arria II Device Family

Arria II Device Architecture

Arria II Device Handbook Volume 1: Device Interfaces and Integration December 2010 Altera Corporation

Arria II Device Architecture

Arria II devices include a customer-defined feature set optimized for cost-sensitive

applications and offer a wide range of density, memory, embedded multiplier, I/O,

and packaging options. Arria II devices support external memory interfaces and I/O

protocols required by wireless, wireline, broadcast, computer, storage, and military

markets. They inherit the 8-input ALM, M9K and M144K embedded RAM block, and

high-performance DSP blocks from the Stratix®IV device family with a

cost-optimized I/O cell and a transceiver optimized for 6.375 Gbps speeds.

Figure 1–1 and Figure 1–2 show an overview of the Arria II GX and Arria II GZ device

architecture, respectively.

Figure 1–1. Architecture Overview for Arria II GX Devices

Arria II GX FPGA Fabric

(Logic Elements, DSP,

Embedded Memory, Clock Networks)

All the blocks in this graphic are for the largest density in the

Arria II GX family.The number of blocks can vary based on

the density of the device.

PLL

DLL

PLL

Transceiver

Blocks

Plug and Play PCIe hard IP

1, 2,

4, and

High-Speed Differential I/O,

General Purpose I/O, and

Memory Interface

High-Speed Differential I/O,

General Purpose I/O, and

Memory Interface

High-Speed Differential I/O,

General Purpose I/O, and

Memory Interface

High-Speed

Differential I/O

with DPA,

General

Purpose

I/O, and

Memory

Interface

High-Speed

Differential I/O

with DPA,

General

Purpose

I/O, and

Memory

Interface

High-Speed Differential I/O,

General Purpose I/O, and

Memory Interface

××

Chapter 1: Overview for the Arria II Device Family 1–7

Arria II Device Architecture

December 2010 Altera Corporation Arria II Device Handbook Volume 1: Device Interfaces and Integration

High-Speed Transceiver Features

Arria II GX devices integrate up to 16 transceivers and Arria II GZ devices up to 24

transceivers on a single device. The transceiver block is optimized for cost and power

consumption. Arria II transceivers support the following features:

■Configurable pre-emphasis and equalization, and adjustable output differential

voltage

■Flexible and easy-to-configure transceiver datapath to implement proprietary

protocols

■Signal integrity features

■Programmable transmitter pre-emphasis to compensate for inter-symbol

interference (ISI)

■User-controlled receiver equalization with up to 7 dB (Arria II GX) and

16 dB (Arria II GZ) of high-frequency gain

■On-die power supply regulators for transmitter and receiver PLL charge pump

and voltage-controlled oscillator (VCO) for superior noise immunity

■Calibration circuitry for transmitter and receiver on-chip termination (OCT)

resistors

Figure 1–2. Architecture Overview for Arria II GZ Device

Notes to Figure 1–2:

(1) Not available for 780-pin FBGA package.

(2) Not available for 780-pin and 1152-pin FBGA packages.

General Purpose

I/O and Memory

Interface

400 Mbps-6.375 Gbps CDR-based Transceiver

General Purpose I/O and 150 Mbps-1.25 Gbps

LVDS interface with DPA and Soft-CDR

Transceiver

Block

Transceiver

Block

Transceiver

Block PCI Express

Hard IP Block

General Purpose

I/O and Memory

Interface

PLL

(2)

PLL

(1)

PLL PLL

General Purpose

I/O and Memory

Interface

General Purpose

I/O and Memory

Interface

PLL PLL

Arria II GZ FPGA Fabric

(Logic Elements, DSP,

Embedded Memory,

Clock Networks)

Transceiver Block

General Purpose I/O and

High-Speed LVDS I/O

with DPA and Soft CDR

General Purpose

I/O and

High-Speed

LVDS I/O with

DPA and Soft CDR

PLL

(2)

PLL

(1)

Transceiver

Block

Transceiver

Block

Transceiver

Block

General Purpose

I/O and

High-Speed

LVDS I/O with

DPA and Soft CDR

General Purpose

I/O and

High-Speed

LVDS I/O with

DPA and Soft CDR

General Purpose

I/O and

High-Speed

LVDS I/O with

DPA and Soft CDR

1–8 Chapter 1: Overview for the Arria II Device Family

Arria II Device Architecture

Arria II Device Handbook Volume 1: Device Interfaces and Integration December 2010 Altera Corporation

■Diagnostic features

■Serial loopback from the transmitter serializer to the receiver CDR for

transceiver physical coding sublayer (PCS) and PMA diagnostics

■Parallel loopback from the transmitter PCS to the receiver PCS with built-in self

test (BIST) pattern generator and verifier

■Reverse serial loopback pre- and post-CDR to transmitter buffer for physical

link diagnostics

■Loopback master and slave capability in PCIe hard IP blocks

■Support for protocol features such as MSB-to-LSB transmission in a

SONET/SDH configuration and spread-spectrum clocking in a PCIe

configuration

Table 1–5 lists common protocols and the Arria II dedicated circuitry and features for

implementing these protocols.

1For other protocols supported by Arria II devices, such as SONET/SDH, SDI, SATA

and SRIO, refer to the Transceiver Architecture in Arria II Devices chapter.

Table 1–5. Sample of Supported Protocols and Feature Descriptions for Arria II Devices

Supported Protocols Feature Descriptions

PCIe

■Complete PCIe Gen1 and Gen2 protocol stack solution compliant to PCIe Base

Specification 2.0 that includes PHY/MAC, Data Link, and Transaction layer circuitry

embedded in the PCIe hard IP blocks.

■PCIe Gen1 has ×1, ×2, ×4, and ×8 lane configurations. PCIe Gen2 has ×1, ×2, and ×4

lane configurations. PCIe Gen2 does not support ×8 lane configurations

■Built-in circuitry for electrical idle generation and detection, receiver detect, power state

transitions, lane reversal, and polarity inversion

■8B/10B encoder and decoder, receiver synchronization state machine, and ±300 PPM

clock compensation circuitry

■Options to use:

■Hard IP Data Link Layer and Transaction Layer

■Hard IP Data Link Layer and custom Soft IP Transaction Layer

XAUI/HiGig/HiGig+

■Compliant to IEEE P802.3ae specification

■Embedded state machine circuitry to convert XGMII idle code groups (||I||) to and from

idle ordered sets (||A||, ||K||, ||R||) at the transmitter and receiver, respectively

■8B/10B encoder and decoder, receiver synchronization state machine, lane deskew, and

±100 PPM clock compensation circuitry

Gbe

■Compliant to IEEE 802.3 specification

■Automatic idle ordered set (/I1/, /I2/) generation at the transmitter, depending on the

current running disparity

■8B/10B encoder and decoder, receiver synchronization state machine, and ±100 PPM

clock compensation circuitry

CPRI/OBSAI

■Transmit bit slipper eliminates latency uncertainty to comply with CPRI/OBSAI

specifications

■Optimized for power and cost for remote radio heads and RF modules

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