Advantech MIC-3756 Manual de usuario
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Copyright Notice
This document is copyrighted, 2003. All rights are reserved. The
original manufacturer reserves the right to make improvements to the
products described in this manual at any time without notice.
No part of this manual may be reproduced, copied, translated or
transmitted in any form or by any means without the prior written
permission of the original manufacturer. Information provided in this
manual is intended to be accurate and reliable. However, the original
manufacturer assumes no responsibility for its use, nor for any
infringements upon the rights of third parties which may result fromits
use.
Acknowledgments
MS-DOS, Windows®, Microsoft® Visual C++ and Visual BASIC are
trademarks of Microsoft® Corporation. Intel® and Pentium® are
trademarks of Intel Corporation. Delphi and C++ Builder are
trademarks of Borland Software Corporation.
CE notification
The MIC-3756, developed by ADVANTECH CO., LTD., has passed
the CE test for environmental specifications when shielded cables are
used for external wiring. We recommend the use of shielded cables.
This kind of cable is available from Advantech. Please contact your
local supplier for ordering information.
On-line Technical Support
For technical support and service, please visit our support website at:
http://www.advantech.com/support
Part No.2003375600 1st Edition
Printed in Taiwan October 2003
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Contents
1. Introduction ·······································································································3
1.1 Features ··································································································3
1.2 Specifications ························································································6
2. Hardware Configuration···············································································9
2.1 Initial Inspection····················································································9
2.2 Hardware Installation········································································11
2.3 Board Layout ·······················································································14
3. Pin Assignment and Jumper Setting···················································19
3.1 Pin Assignment ···················································································19
3.2 Location of Jumpers and DIP switch···········································22
3.3 Isolated Digital Input Connections················································23
3.4 Isolated Digital Output Connections ············································24
3.5 Field Wiring Considerations····························································26
4. Operations········································································································29
4.1 Interrupt Function···············································································29
4.2 Board ID································································································33
4.3 Channel-Freeze Function································································35
4.4 Counter Function················································································38
Appendix A. Specifications···········································································45
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Appendix B. Register Structure & format···············································47
B.1 Register Structure··············································································47
B.2 Register Format··················································································48
Appendix C. Waveform of Counter Mode ···············································51
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Tables
Table 3-2 JP3 Power on configuration after hot reset········································24
Table 4-1 Interrupt control register bit map·························································30
Table 4-2 Latch port data disable/enable control bit ··········································31
Table 4-3 Interrupt disable/enable control bit values·········································31
Table 4-4 Interrupt triggering edge control bit values········································31
Table 4-5 Interrupt flag bit values··········································································32
Table 4-6 Board ID register····················································································33
Table 4-7 Board ID setting······················································································34
Table 4-8 JP2 Channel-Freeze function input mode···········································36
Table 4-9 Channel-Freeze function register·························································37
Table 4-10 Channel-Freeze function bit value·····················································37
Table 4-11 Counter Mode Register········································································38
Table 4-12 Counter Read Register········································································39
Table 4-13 Set Value Register···············································································39
Table 4-14 Counter Reset Register········································································39
Table 4-15 INT Register of Counter·····································································40
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Figures
Fig.2-1MIC-3756 board layout············································································14
Fig.3-1I/O Connector pin assignments for the MIC-3756 ······························20
Fig.3-2Location of Jumpers and DIP switch on MIC-3756····························22
Fig.3-3 Isolated digital input connection·····························································23
Fig.3-4 Isolated Digital Output Connection························································25
Fig.4-2 The wiring in wet/dry contact input mode············································36
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Introduction
1
CHAPTER
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1. Introduction
This chapter gives background information on the MIC-3756. It then
shows you how to configure the card to match your application and
prepare it for installation into your system.
The MIC-3756 is a 64-channel Isolated Digital I/O CompactPCI™
DAS Card,which complies with PICMG 2.0 R2.1 CompactPCI
specifications.The MIC-3756 features a unique circuit design and
complete functions for data acquisition and control. It is a powerful
data acquisition (DAS) card for the CompactPCI bus.
1.1 Features
wCPCI bus specification 2.1 compliant
wCPCI 3U size card
w32 isolated digital input channels
w32 isolated digital output channels
wHigh-voltage isolation for input/output channels (2,500 VDC )
wWide input range (10 ~ 50 VDC )
wWide output range (5 ~ 40 VDC )
wHigh-sink current on isolated output channels (200 mA max./
channel)
wHigh over-voltage protection (70 VDC ) for input channels
wBoard ID
wOutput status read-back for output channels
wDigital output value retainedafter hot system reset
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wChannel-Freeze function for output channels
wOne independent 16-bit UP Counter
w2 Counter Clock Source selectable
w1MHz input counter frequency on broad
wI/O address automatically assigned by PCI plug-and-play
wOS supported: Windows® NT, Windows® 95/98, Windows®
2000, Windows® XP
wInterrupt status register for increased performance
The Advantech MIC-3756 DAS card offers the following main
features:
Robust Isolation
The MIC-3756 features a robust isolation protection for applications
in industrial, lab and machinery automation. The MIC-3756 can
durably withstand voltages up to 2,500 VDC, preventing your host
system from any incidental harms. Even with an input voltage rising
up to 70 VDC, the input channels of MIC-3756 can still manage to
work properly albeit only for a short period of time.
Wide Input/Output Range
The MIC-3756 has a wide range of input voltage from 10 to 50 VDC,
which is suitable for most industrial applications with 12 VDC, 24
VDC and 48 VDC input voltage. The MIC-3756 also features a wide
output voltage ranging from 5 to 40 VDC, suitable for most industrial
applications with 12 VDC / 24 VDC output voltage. In the mean time,
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