iDAQ-731_751_763D User Manual x
Figure 3.5 Digital input both edges interrupts............................ 21
Figure 3.6 Digital input pattern match interrupt for pattern
“10xx0100”. .............................................................. 22
Figure 3.7 Digital input debounce filter...................................... 22
3.3.2 Instant Digital Input Acquisition................................................... 23
Figure 3.8 Instant digital input acquisition. ................................ 23
3.3.3 Buffered Digital Input Acquisition................................................ 23
Figure 3.9 Digital input buffered (hardware-timed) acquisition.. 23
3.4 Configuration for Buffered Digital Input Acquisition ................................ 24
3.4.1 One-buffered Digital Input Acquisition ........................................ 24
Figure 3.10Post-trigger acquisition............................................. 24
Figure 3.11Post-trigger acquisition with delay............................ 24
Figure 3.12Pre-trigger acquisition. ............................................. 25
Figure 3.13About-trigger acquisition........................................... 25
3.4.2 Streaming Digital Input Acquisition............................................. 26
Figure 3.14Streaming acquisition. .............................................. 26
3.4.3 Retriggerable Digital Input Acquisition........................................ 26
Figure 3.15Post-trigger acquisition with retrigger. ...................... 26
Figure 3.16Pre-trigger acquisition with retrigger......................... 27
Figure 3.17About-trigger acquisition with retrigger..................... 27
Figure 3.18Streaming acquisition with retrigger ......................... 27
3.5 Digital Output .......................................................................................... 28
3.5.1 Static Digital Output Update ....................................................... 28
Figure 3.19Static digital output update. ...................................... 28
3.5.2 Buffered Digital Output Waveform Generation ........................... 28
Figure 3.20Buffered digital output waveform generation............ 28
Figure 3.21Start and stop of the digital output waveform genera-
tion............................................................................ 29
Figure 3.22Start and stop of the digital output waveform generation
with delay. ................................................................ 29
3.5.3 Digital Output Fail-Safe Function................................................ 29
3.6 Configuration for Buffered Digital Output Generation ............................. 30
3.6.1 One-Buffered Digital Output Generation..................................... 30
Figure 3.23One-buffered generation. ......................................... 30
Figure 3.24One-buffered generation with delay. ........................ 30
3.6.2 Streaming Digital Output Generation.......................................... 31
Figure 3.25Streaming generation. .............................................. 31
3.6.3 Retriggerable Digital Output Generation..................................... 31
Figure 3.26One-buffered generation with retrigger. ................... 31
Figure 3.27Streaming generation with retrigger. ........................ 32
3.7 Device Description and Configuration..................................................... 33
Figure 3.28Device description shown in Navigator. ................... 33
Chapter A Specifications.................................... 35
A.1 Isolated Digital Input (iDAQ-731) ............................................................ 36
A.2 TTL Digital Input (iDAQ-751) .................................................................. 36
A.3 Universal Digital Output (iDAQ-731) ....................................................... 37
A.4 TTL Digital Output (iDAQ-751)................................................................ 37
A.5 Solid-State Relay (SSR) Output.............................................................. 37
A.6 General ................................................................................................... 38
A.7 Function Block ........................................................................................ 39
Chapter B System Dimensions.......................... 41
B.1 iDAQ Modules......................................................................................... 42
