Advanced Digital SUPER SIX S-100 Manual de usuario

SUPER

SIX

S-1.

00

Single Board

Computer

-Technical -

Manual

«j>

ADVANCED

DIGITAL

USA OFFICE

5432 PRODUCTION DRIVE

HUNTINGTON

BEACH,

CA

92649

TELEPHONE : (714) 891-4004

TELEX: 183210 ADVANCED

HTBH

CORPORATION

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OFFICE

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UNITED

KINGDOM

409-0077 / 409-3351

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]

SUPER

SIX™

S-lOO Single Board

Computer

Technical

Manual

June

1,

1983

ADVANCED

DIGITAL

CORPORATION

TABLE.

OF

CONTENTS

SECTION TITLE

SECTION I - JNTRODUCTION

1.1

Purpose

1.2 Equipment Overvie'W

1.3

Document

Organization

1.4 List

of

Acronyms

1.5

Document

Maintenance

1.6 Theory

of

Operation

SECTION

II

-OPERATION

2.1

2.2

2.3

2.4

2.5

2.6

2.7

2.8

2.9

2.10

2.11

2.12

2.13

2.14

2.15

2.9.1

2.9.2

2.9.3

2.9.4

Floppy Disk

Controller

128K Dynamic RAM

System

Monitor EPl{OM

Serial

Ports

Para1Jel

Ports

Real

Time

Interrupt

Clock

S-

100 Bus

Interface

Baud

Rate

Jumper

EPROM

and

Monitor

Operations

EPR

OM

Enable

and

Disable

Monitor

Sign-on

Monitor

Commands

Cold

Start

Program

RAM

Organization

Z80A DMA

Features

PSNET/1

Operation

PSNET

/PAR

Operation

Synchronous

Operations

Power

Consumption

SECTION

HI

-INPUT/OUTPUT

POR

TS

3.1

Input/Output

Port

Assignments

3.2

Input/Output

Descriptions

3.2.1

Port

00

3.2.2

Port

01

3.2.3

Port

02

3.2.4

Port

03

3.2.5

Port

04

3.2.6

Port

0.5

3.2.7

Port

06

3.2.8

Port

07

3.2.9

Port

08

3.2.10

Port

09

3.2.1 1

Port

OA

3.2.12

Port

DB

3.2.13

Port

OC

3.2.14

Port

OD

3.2.15

Port

DE

3.2.16

Port

OF

3.2.17

Ports

10-13

PAGE

1

2

3

4

5

7

.7,

7

8

10

11

12

13

14

.

15

AU

information

contained

in

this

document

is

the

property

of

Advanced

DigitaJ

Corporation.

TABLE

OF

CONTENTS

(continued)

SECTION TITLE

PA~E

3.2.18

Port

14

16

3.2.18.1

Port

14

Read

Opera

tion

16

3.2.19

Port

15

17

3.2.19.1

Port

15 l{ead

Operation

17

3.2.19.2

Port

15 Wri

te

Operation

17

3.2.20

Ports

16

and

17

3.2.20.1

Port

17

\\I

ri

te

Operation

18

3.2.20.2

Port

17

W

rite

Operation

l~

3.2.21

Ports

18-1B

21

j

SECTION

IV

-

JUMPER

CONNECTIONS

22

4.1

Jumper

Definitions

22

4.2

Jumper

Descriptions

23

4.2.1

Jumper

A 23

4.2.2

Jumper

B 23

4.2.3

Jumper

C 23

4.2.4

Jumper

D 24

4.2.5

Jumper

E

24

4.2.6

Jumper

G 24

4.2.7

Jumpers

Hand

T

24

4.2.8

Jumper

J6

24

4.2.9

Jumper

R25 25

4.2.10

Jumper

J7

25

4.2.11

Jumpers

P, N,

M,

K,

J,

R, S,

and

F

2.5

4.3

Factory

and

OEM

Installed

Jumpers

26

4.3.1

8-lnch

Floppy Disk

Drive

26

4.3.2

~hugart

SA800/801 Disk

Drive

26

4.3.3

Shugart

850 Disk Ori

ve

27

4.3.4

MFE Model 700 Disk

Drive

27

4.3.5

Tandon Slim Line Disk

Drive

27

4.3.6

NEC Model FD1160 Disk

Drive

28

4.3.7

QUME

Data

Track

Disk

Drive

28

4.3.8

Tandon 5.2.5 Inch Disk

Drive

28

4.3.9

Mitsubishi Model 2894 Disk

Drive

28

4.3.10

Mitsubishi Model 2896 Disk

Drive

28

4.3.11

Shugart

SA 860 Disk

Drive

28

4.3.14

Siemens

FDD-I00-8

Disk

Drive

29

4.3.16

Qume

Trak

592

5.25

Inch Disk

lJrive

29

4.3.17

All

Other

Disk

Drives

29

SECTION V -

EXTERNAL

CONNEC10R

PINS 30

5.1

Connector

S-100

30

5.2

Connector

J 2

31

5.3

Connector

J3

32

5.4

Connector

J 4 33

5.5

Connector

J5

33

TABLE

OF

CONTENTS

(continued)

SECTION TITLE

APPENDIX

A -

Z80A/Z80B

SIO

AND

DART

APPEN

DIX B -

Z80A/Z80B

PIO

APPENDIX

C -

Z80A/Z80B

eTC

APPENDIX

D -

Z80A/Z80B

CPU

APPENDIX

E -

280

DMA

APPENDIX

F -

FLOPPY

DISK

CONTROLLER

APPENDIX

G -

FLOPPY

DISK El{ROR CODES

APPENDIX

H -

APPLICATION

NOTES

APPENDIX

I -

SUPER

SIX

WARRANTY

APPENDIX

J

-PARTS

LAYOUT

AND

LIST

APPENDIX

K - PLL

REALIGNMENT

APPENDIX

L -

PSNET/l

SCHEMATICS

APPENDIX

M - PSNET

/PAR

SCHEMATICS

APPENDIX

N -

SUPER

SIX SCHEMATICS

FIGURE

NO.

2-1

2-2

TABLE NO.

1-1

2-1

2-2

3-1

3-2

4-1

5-1

5-2

5-3

5-4

5-5

LIST

OF

FIGURES

TITLE

SUPER

SIX

Interface

To

the

S-100

Bus

SUPER

SIX RAM

Configuration

LISl

OF

TABLES

TITLE

List

Of

Acronyms

SUPER

SIX Baud

Rate

Jumper

Settings

Monitor

Commanas

For

the

SUPER

SIX

I/O

Port

Assignments

For

the

SUPER

SIX

SUPER SIX

Port

18 Baud

Rate

Settings

SUPER

SIX

Jumpers

and

Abbreviated

Functions

SUPER

SIX J I

Connector

Functions

SUPER

SIX

J2

Connector

Functions

SUPER SIX

J3

Connector

Functions

SUPER

SIX

J4

Connector

Functions

SUPER

SIX

J5

Connector

Functions

PAGE

6

11

PAGE

2

7

9

13

21

22

30

31

32

33

SECTION I

INTRODUCTION

1.1

PURPOSE

This Manual

provides

the

technical

information

necessary

to

mstall,

uperate

dna maintair.

the

SUPER

SIX

singleboard

computer

by

Advanced Digital

Corporation.

1.2 EQUIPMENT OVER

VIEW

SUPER SIX,

produced

by Advanced

Digital

Corporation,

is

the

first

single board

computer

for

the

S-IOO bus running

at

6MHz. Without

the

S-100 bus

the

SUPER

SIX

can

also

run.

as

a

standalone

computer

executing

a single

user

CP/M 2.2

or

3.0,

or

a

multiuser

MP

/M,

OASIS,

or

TurboDOS

operating

system.

SUPER

SIX

runs

substantially

faster

than

any

other

S-l

00 single board

computer

a

vialable

in

the

market.

The SUPER

SIX

contains

the

following

set

of

capabilities:

1.

280B CPU

operating

at

6MH2

2. 128K

of

dynamic

bank

se

lect

RAM

arranged

in

16k

banks

3. Floppy Disk

Controller

which supports

the

8-inch

and 5.25-inch disk

drives

simultaniously

4.

2/4

K of shadow EPROM (Monitor)

5. 2

serial

I/O

(RS-232)

ports

offering

software

or

hardware

selectable

baud

rate,

280B DART

6. 2

parallel

ports

(280B PIO)

7.

Real

time

clock

(280B CTC)

8.

DM

A

controller

(280

DM

A)

9. Extended addressing: A16-A23

10. Single 5 volt supply on

board

11.

One-year

warranty

12.

Free

copy of CP/M 2.2 BIOS supplied.

* NOTE:

Items

5 and 6

require

external

adaptation

for

RS-232 and

Centronics.

The

adapter

boards

contain

a

DB-25

connector

on a 2-inch by 2-inch board

attached

to

the

back

panel·of

the

5-100

system

(MODEM and RS 422

Paddle

cards

are

also

available).

-1-

1.3 "

This

document

is organizt'd

inh'

')

sc\.·t i,-'Ils

..

md

14

.lppcndices.

Section

I

serves

as

an

introductioll

to

tht'

entire

document,

stating

the

purpose

of

the

document

and providing

an

introduction

to

the

SuPER

SIX

single

board

computer.

This

section

also

provides

a list

of

acronyms

used in

the

document

and

provides

a

statement

on

the

responsibilities

of

document

maintenance.

Section

II

provides

a

description

of

the

operations

of

aU

components

associated

with

the

SUPER SIX

single

board

computer.

Section

III

lists

aU

SUPER

SIX

input/output

ports

and

defines

the

assignments

and

functions

of

each

port.

Section

IV

lists

and

defines

aJJ

SUPER SIX

jumper

connections.

This

section

includes

the

jumper

,assignments

for

factory

(OEM)

installed

jumpers.

Section

V

describes

the

external

connector

pins

for

SUPER SIX

connectors

J 1

through

J5.

The

appendices

provide

supplemental

material

to

the

body

of

the

text

and

are

referenced

in

the

text

at

the

associated

points.

1.4 LIST

OF

ACRONYMS

Table 1

-1

provides

a listing and

description

of

the

acronyms

used within

this

text.

ACRONYM

DESCRIPTIO~

CPU

Central

Processor

Unit

CTC ControJJer

/Timer

Circui

t

DART Dual Asynchronous

Receiver/Transmitter

DMA

Direct

Memory

Access

EPROM

ElectricaUy

Erasable

Programmable

Read-Only

Memory

FDe Floppy Disk

Controller

IEEE

Institute

of

Electrical

and

Electronic

Engineers

MP/M Multiuser

Program

For

Microcomputers

OEM Original

Equipment

Manufacturer

PIO ParaUel

Input/Output

PROM

Programmable

Read-Only Menlory

Table 1-1. List

of

Acronyms

-2-

Table

I-I.

List

of

Acronyms (Continued)

ACRONYM

DE~CRIPTIOi\

1.5

RAM

Random

Access

Memory

SIO

Serial

Input/Output

TTL

Transistor-transistor

Logic

TurboDOS A Multiuser

Networking

Operating

System used

as

software

with

the

SUPER

SIX

DOCUMENT MAINTENANCE

This

document

is

the

property

of Advanced Digital

Corporation,

who

is

responsible

for

its

content.

Any

modifications

made

to

this

manual

must

be

made

with

the

express

written

approval

of

Advanced

Digital

Corporation.

1.6 THEORY

OF

OPERATION -

ST

ART-UP PROCEDURE

The SUPER

SIX

Single

board

computer

is shipped

configured

for

19.

installation

procedure

is

as

follows: baud

rate.

The

1.

Plug

the

PSNET

/1

to

connector

J5.

Use

caution;

pin 1 is

marked.

2.

Connect

the

CRT. Pins 2, 3, 5, 7,

and

20

must

be

used; no

parity

must

be

specified,

3. Apply

power

to

the

system.

The

monitor

message

shown in

subsection

2.9.2

appears.

Check

the

CRT

baud

rate-

if

9600 baud

is

required,

unplug

jumper

area

J7,

pin 7-8.

4. Install

the

floppy disk

cable,

load

the

CP/M

diskette,

and

bootstrap

the

system.

Note:

CP/M

is

shipped

configured

for

64K

bytes

of

memory.

The

parallel

port

is

configured

as

the

default

printer.

1024

bytes

per

sector

read/writes

are

also'

supported

(or DMA). The plus

8V

and

the

plus/minus

16

V

on

the

S-lOO bus

must

be

verified

prior

to

installing

the

SUPER SIX board.

-3-

SECTION

II

OPERATION

This

section

describes

the

opera

tion

01

all

SUPER

SIX

<;:ompone.nts.

2.1

FLOPPY

DISK

CONTROLLER

The

floppy disk

controiJer

can

access

up

to

four

8-inch

or

four

5.25-inch

disk

drives

or

any

combination

of

the

two.

The

controller

can

read

and

write

ISIv1

3740

single

density

format

and double

density

1024

sector-SIze

formats.

Data

transfer

is

performed

via

Direct

Memory

Access

(DMA). Due

to

the

simultanious

operation

capability

of

the

SUPER

SIX

the

format

compatibility

problems

with

5.25-inch

disks

have

been

eliminatea.

The

floppy

disk

controller

used is

the

WD27~3.

The WD2793 has

on-chip

PLL

,data

separators

and

on-chip

write

pre-compensation

logic.

Adjustments

for

PLL

are

factory

set

dnu

write

pre-compensation

has

been

provided

with

the

SUPER SIX. 50 Pin

and

34 pin

connectors

are

available

for

8-inch

and

5.25-inch

disk

drives

respectively.

2.2

NOTE:

Customer

adjustment

of

trim

pots

may

result

in

cancellation

of

warranty.

THE 128K DYNAMIC RAM

The 128K RAM

array

can

be

switched

ON

and

OFF

in

16K

increments,

(0-16K, 16K-32K,

32K-48K, 48K-64K

for

both

banks)

under

soitware

control.

This

feature

allows

the

CPU

to

access

bank

switchable

external

memory on

the

S-IOO bus.

The

memury

has

an

access

time

of

150ns. A

Refresh

operation

is

performed

during Z80 MI

cycles

and

during

\V

AIT

and RESET

states.

The

memory

can

be

accessed

by floppy dIsk via

D~iA,

serial

and

paralle

1'I/O,

or

another

DMA

device

un

the

S-l

00 bus.

*NOTE:

Any

external

DlV1A

device

that

is

using

continous

mode

DMA

cycles

must

transfer

data

at

an

average

rate

of

1501s

per

byte

or

faster

when holding

the

DMA

request

line

for

more

than

1.5I11s.

The RAM row

address

is

the

low

order

address;

therefore

the

entire

RAM

array

is

refreshed

by

DMA

device

every

128

contiguous

memory

cycles.

Under CPM 2.2 or CPM 3.0

the

additional

64K

can

be used

as

a dISk

buffer.

The

·SUPER

SIX

is

ideal

when

operating

in

the

bank

mode

under

CP/M

3.0,

as

128K RAM

is

required.

-4-

\

2.3 SYSTEM

MONIT01<

EPHOM

The

system

monitor

t.PHOM

is

switched

ON

during

reset.

Jt

C~II

t)(~

(jj~~t.Jl(:a

dr,G

(:rlabled

under

software

control.

When

enabled,

the

system

IIluflltor

r(:sjrj(:C)

dt

locations

F800-FFFF

(hex)

(refer

to

subsection

2.9.1.2)

when

using

1716

Ll't<U,\'

or

CIt

locations

FOOO-FFFF

(hex)

when

using

the

2732

EPRL'M.

lhe

~>stelrr

I/lonitur

LP~lIM

contains

the

cold-start

loader

for

CP

/tvl,

MP

/1\1

and

1

urboDl.\).

In .:idunia!I jt Cdn

De

used

to

perform

LOAD,

I/O

READ

and

1/0

'W

RITE

operations.

'When

the

LP1.(,-).vi

is

disablea

no

system

address

space

is

used.

2.4

SERIAL

PUR

IS

A

6MHz

Z801:)

DART

is

used

for

the

two

serial

I/O

ports;

a 2:805 ,)10

or

Z80A DAH T

can

be

used

in

it's

place

(if

a

4MHz

Z80A

DART

is

used

the

CPU

and

all

other

devices

must

also

be

4MHz).

This

allows

asynchronous

serial

data

communication

plus

a

variety

of

interrupt

modes.

Modem

control

signals

are

available

at

each

serial

connector.

There

are

software

selectable

baud

rates

as

well

as

hardware

selectable

baud

rates

(mini-jumpers

J7).

2.5

*

NOTE:

The

serial

ports

are

TTL

and

must

be

connected

to

PSN

ET/

1

(serial

adapter

interface)

for

RS-232

communications.

The

J4

connector

is

for

the

CR

T;

the

J5

connector

is

for

the

serial

printer

or

CH T.

PARALLEL POl{

15

A

6MHz

280B

PIO

is

used

as

the

parallel

port.

The

"A"

channel

of

this

chip

is

used

to

connect

the

parallel

port

connector

(J2)

to

PIO.

This

port

has

an

8-bit

bi-directional

data

line

and

two

hand-shake

lines. 1

he

"13"

port

can

be

split

between

the

parallel

port

connector

and

the

5-100

bus

vectored

interrupts

lines

by

jumper

options.

This

allows

the

port

to

be

used

as

an

additional

paralJel

port,

an

interrupt

controller,

or

both

of

the

above.

In

the

output

mode

the

parallel

ports

can

drive

one

TTL

load.

2.6

REAL

TIME

INTERkUPT

LLOCK

A

6MHz

280B

eTC

is

used

for

providing

a

real

time

system

clock

for

tvlP

/M

or

TurboDOS

operating

systems.

Three

channels

of

the

eTC

are

available

to

the

user

for

jumpering

to

synchronous

baud

rates

or

long

clock

times.

2.7 S-IOO BUS

IN1ERFACE

The

5-100

bus

interface

provides

the

signals

necessary

for

an

8-bit

bus

master

as

described

by

the

lEEE-696

bus

specification.

Vectored

interrupt

lines

VIO-

V

17

are

supported

via

jumper

options

(refer

to

section

I

V)

and

A

16-A23

are

also

supported

via

an

1/0

port.

The

Phantom

line

is

also

implemented

for

the

dynamic

RAM

array.

The SUPEl{

SlX

interface

with

the

S-1

00

bus is

depicted

in

Figure

2-1.

TurboJ..)O~

is

the

registered

trademark

of

Software

2000,

Inc.

CP/M

and

MP

/M

are

the

registered

trademarks

of

Digital

i{esearch,

Inc.

-5-

Advanced Digital SUPER SIX S-100 Manual de usuario

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